3D NAND Memory Openings With Multi-Channel Layout and No Dummy Rows
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Solution Overview
Problem
Current three-dimensional NAND memory devices have limitations in device density due to the presence of dummy rows of inactive semiconductor channels under drain-select-level dielectric isolation structures, which occupy space and reduce efficiency.
Innovation Solution
The formation of plural vertical semiconductor channels in each memory opening, along with the elimination of dummy rows by using a curvature-dependent lateral etch process, increases device density and optimizes the arrangement of memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy rows of inactive semiconductor channels are present under drain-select-level dielectric isolation structures, then device layout is simplified, but device density is reduced
Solution Approach 1:
The invention extracts and removes the dummy rows of inactive semiconductor channels from the device structure. By eliminating these non-functional channels that occupy space under the drain-select-level dielectric isolation structures, the patent increases the effective device density while maintaining the simplified layout approach through selective removal rather than complex reconfiguration
Solution Approach 2:
The invention changes the parameter of channel activity from inactive to active by forming functional semiconductor channels in place of or alongside the dummy rows. This parameter change transforms the space-consuming inactive structures into productive active channels, thereby increasing device density without compromising manufacturing simplicity
2Quantity of substance
If multiple vertical semiconductor channels are formed in each memory opening, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The invention segments the semiconductor channel formation process into distinct stages: forming the memory film in each memory opening, depositing the semiconductor channel layer, and then performing selective lateral etching to create multiple vertical channels. This segmentation allows complex multi-channel structures to be built through simple, repeatable steps, increasing device density while managing manufacturing complexity
Solution Approach 2:
The invention replaces complex mechanical patterning processes with a curvature-dependent lateral etch process that automatically forms multiple vertical semiconductor channels. This substitution uses chemical etching mechanisms driven by surface curvature differences to create the desired multi-channel structure, simplifying the manufacturing process while achieving high device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density by eliminating unnecessary semiconductor channels and optimizing the layout, leading to more efficient use of space and improved performance in three-dimensional memory devices.
Implementation Method 1
performing a curvature-dependent lateral etch process that etches surfaces of the semiconductor channel layer having a lower curvature at a higher etch rate than surfaces of the semiconductor channel layer having a higher curvature
Data Source
AI summary
A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels.