Bonded 3D Memory Die Assembly With Through-Stack Via Alignment
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Solution Overview
Problem
Existing semiconductor technologies face challenges in efficiently forming bonded semiconductor die assemblies with through-stack via structures, which are crucial for enhancing the performance of three-dimensional memory devices.
Innovation Solution
A bonded semiconductor die assembly is formed by bonding a second three-dimensional memory die to a first three-dimensional memory die, both of which include alternating stacks of insulating and electrically conductive layers, memory structures, and stepped dielectric material portions. The electrically conductive layers in each die have varying lateral extents along a horizontal direction, with those in the first die decreasing and those in the second die increasing with vertical distance from the driver circuit devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple three-dimensional memory dies are stacked to increase memory density, then the memory capacity is improved, but the complexity of forming reliable vertical interconnections increases
Solution Approach 1:
The patent divides the bonding interface into multiple bonding regions, each containing a subset of through-stack via structures. This segmentation allows different regions to be formed and bonded independently, reducing the overall complexity of forming all interconnections simultaneously while achieving high memory capacity through stacking.
Solution Approach 2:
The patent forms through-stack via structures and bonding pads on each memory die before the stacking process. This preliminary preparation of interconnection structures enables efficient bonding when dies are stacked, as the connection pathways are already established rather than requiring complex post-bonding formation processes.
2Reliability
If through-stack via structures are formed to enable vertical interconnections, then the electrical connectivity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent introduces stepped dielectric material portions as intermediary structures between the alternating conductive and insulating layers. These stepped portions create defined bonding regions that guide and align the through-stack via structures, ensuring precise electrical connectivity without requiring extreme manufacturing precision for direct via-to-via alignment.
Solution Approach 2:
The patent creates different bonding regions with varying properties - some regions have through-stack via structures while others have different configurations. This local differentiation allows optimization of electrical connectivity in critical areas while reducing overall manufacturing complexity, as not all regions require the same level of precision.
3Reliability
If alternating stacks of conductive and insulating layers are used to form memory structures, then the three-dimensional memory performance is improved, but the device complexity increases
Solution Approach 1:
The patent designs the alternating stack of conductive and insulating layers to serve multiple functions: storing memory data, providing electrical interconnections between stacked dies, and creating bonding regions for assembly. This multi-functionality reduces the need for separate dedicated interconnection layers, thereby reducing overall device complexity while maintaining high memory performance.
Data Source
AI summary
A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.