Dual-Gate Array Substrate Layout for Higher Pixel Aperture
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Solution Overview
Problem
The aperture ratio of pixels in existing dual gate array substrates is limited, which affects the performance of high-resolution display panels.
Innovation Solution
A dual gate array substrate design featuring groups of dual gate lines, data lines, and pixel pairs on a substrate, with common electrode lines connecting common electrodes of adjacent pixel units, and the common electrode and source/drain electrode layers being insulated from each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a dual gate array substrate is used to reduce the number of data lines and driving circuit cost, then the product cost is reduced, but the aperture ratio of the pixel is adversely affected
Solution Approach 1:
The patent introduces a new spatial dimension by stacking common electrode lines in multiple layers (first common electrode line layer and second common electrode line layer) at different heights. This vertical arrangement allows the common electrode lines to connect to common electrodes of pixel units without occupying horizontal pixel area, thereby maintaining high aperture ratio while achieving dual gate functionality with reduced data lines
Solution Approach 2:
The patent introduces common electrode lines as intermediary elements that are positioned between the data lines and the common electrodes of pixel units. These common electrode lines act as mediators to transmit signals to the common electrodes without interfering with the data line connections to pixel electrodes, thus enabling the dual gate structure to achieve both cost reduction and high aperture ratio
Data Source
AI summary
A dual gate array substrate includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs and a plurality of common electrode lines, each common electrode line is arranged between two pixel units in a same pixel pair; and a layer where the common electrode line is located and a layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other.