Pixel With Dual-Capacitance Dielectric Layer for Charge Transfer
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Solution Overview
Problem
Pixels with vertical transfer gates face issues such as electron transport lag and electron back-scattering, which limit the increase in pixel density and image resolution.
Innovation Solution
A pixel design featuring a semiconductor substrate with a trench and a dual-capacitance dielectric layer, where the photodiode region has a bottom and top section, and the floating diffusion region extends to a junction depth less than the trench depth, with a dielectric layer lining the trench, forming capacitors with varying thicknesses to enhance charge transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical transfer gates are used to increase pixel density, then pixel density increases, but electron transport lag and back-scattering occur
Solution Approach 1:
The dielectric layer is segmented into two distinct regions with different thicknesses: a first region with a first thickness and a second region with a second thickness greater than the first. This segmentation creates two different capacitance values that work together to improve electron transfer efficiency while maintaining high pixel density with vertical transfer gates.
Solution Approach 2:
Different regions of the dielectric layer are given different local properties (different thicknesses) to perform different functions. The thinner first region provides one capacitance characteristic while the thicker second region provides another, allowing optimization of electron transfer at different locations within the pixel structure.
2Measurement precision
If pixel size is decreased to increase pixel density, then maximum attainable resolution increases, but electron transport problems worsen
Solution Approach 1:
The dielectric layer is divided into two thickness regions that create different capacitance effects, allowing the pixel structure to maintain effective electron transfer performance even as pixel size decreases and pixel density increases.
Solution Approach 2:
The capacitance parameters are changed by varying the dielectric layer thickness in different regions. This parameter modification optimizes the electrical characteristics of the vertical transfer gate, reducing electron back-scattering and transport lag while enabling smaller pixel sizes for higher resolution imaging.
3Ease of operation
If photodiode and floating diffusion are laterally displaced with transfer gate therebetween, then charge transfer is enabled, but pixel density cannot be further decreased
Solution Approach 1:
The invention transitions from horizontal charge transfer to vertical charge transfer by orienting the transfer gate vertically. This dimensional change allows charge transfer to occur in the vertical direction rather than lateral direction, enabling further reduction of pixel size and increase in pixel density while maintaining charge transfer capability.
Solution Approach 2:
The dielectric layer is given different local thicknesses in different vertical regions to optimize the vertical charge transfer process, with the thicker second region providing enhanced capacitance where needed in the vertical transfer path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-capacitance dielectric layer reduces electron transport lag and back-scattering, facilitating improved charge transfer and increased pixel density, thereby enhancing image resolution.
Implementation Method 1
A top region of the dielectric layer is between the planar region and the junction depth has a top thickness. A bottom region of the dielectric layer is between the photodiode depth and the trench depth, and has a bottom thickness that exceeds the top thickness.
Implementation Method 2
Light reaching the photodiode region generates photoelectrons.
Data Source
AI summary
A pixel includes a semiconductor substrate, a photodiode region, a floating diffusion region, and a dielectric layer. The substrate has a top surface forming a trench lined by the dielectric layer, and having a trench depth relative to a planar region of the top surface. The photodiode region is in the substrate and includes a bottom photodiode section beneath the trench and a top photodiode section adjacent to the trench, adjoining the bottom photodiode section, and extending toward the planar region to a photodiode depth less than the trench depth. The floating diffusion region is adjacent to the trench and has a junction depth less than the trench depth. A top region of the dielectric layer is between the planar region and the junction depth. A bottom region of the dielectric layer is between the photodiode depth and the trench depth, and thicker than the top region.