RFSOI Superlattice Structure for Carrier Mobility and Interface Quality
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Solution Overview
Problem
Current semiconductor devices face limitations in achieving enhanced performance due to challenges in carrier mobility and material diffusion, despite advancements in strained materials and superlattice structures.
Innovation Solution
The method involves forming a superlattice layer on a donor semiconductor wafer with ion implantation and ion beam treatment to create a separation layer, followed by bonding with a base semiconductor wafer, which enables the formation of an active semiconductor layer with improved mobility and reduced scattering effects, utilizing atomic layer deposition techniques to control the non-semiconductor monolayers within the crystal lattice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained material layers of silicon, silicon-germanium, and relaxed silicon are used to enhance carrier mobility, then device speed and performance are improved, but material diffusion and interface quality degradation occur
Solution Approach 1:
A superlattice layer is introduced as an intermediary between the strained silicon layer and the buried oxide layer. This superlattice acts as a buffer that prevents material diffusion while maintaining the tensile strain in the channel region, thereby preserving both high carrier mobility and interface quality.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including strained silicon, relaxed silicon, silicon-germanium, and superlattice layers. Each layer serves a specific function: the strained silicon provides high mobility, the relaxed silicon releases strain, and the superlattice maintains interface quality, collectively resolving the contradiction between speed and reliability.
2Speed
If superlattice structures are implemented to reduce alloy scattering and enhance mobility, then charge carrier mobility is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The superlattice structure is segmented into multiple thin layers of alternating materials (e.g., silicon and germanium) with precise thickness control. This segmentation allows for reduced alloy scattering and enhanced mobility while maintaining a manageable manufacturing process through sequential deposition techniques.
Solution Approach 2:
The patent optimizes parameters such as layer thickness, material composition ratios, and deposition conditions to achieve the desired mobility enhancement. By carefully controlling these parameters, the complex superlattice structure can be manufactured with standard semiconductor processing techniques, reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility by reducing Coulomb scattering and improving interface quality, while also providing piezoelectric and ferroelectric properties, leading to improved performance in semiconductor devices.
Implementation Method 1
This approach enhances charge carrier mobility by reducing Coulomb scattering
Implementation Method 2
performing ion implantation on the donor semiconductor wafer to create a separation layer
Implementation Method 3
providing piezoelectric and ferroelectric properties
Implementation Method 4
providing piezoelectric and ferroelectric properties
Data Source
AI summary
A semiconductor processing method may include forming a superlattice layer on a donor semiconductor wafer, the superlattice including a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include performing ion implantation on the donor semiconductor wafer to create a separation layer below the superlattice layer, forming an oxide layer on a base semiconductor wafer, performing ion beam treatment on the oxide layer, bonding the donor semiconductor wafer to the base semiconductor wafer so that the superlattice layer is adjacent the oxide layer, removing portions of the donor wafer at the separation layer from the donor wafer to define an active semiconductor layer above the superlattice layer, and forming an electronic device(s) in the active layer.