Trap-Rich SOI Substrate for RF Isolation and Low Distortion

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Solution Overview

Problem

Silicon-on-insulator (SOI) substrates with high resistivity handle wafers suffer from parasitic surface conduction and non-linear distortion in RF signals due to accumulation layers, leading to undesirable device cross-talk and frequency isolation issues.

Innovation Solution

A silicon-on-insulator substrate is created with a trap-rich layer, specifically a high-resistivity base layer containing a trap-rich region with arsenic diffused within, a silicon dioxide layer, and a transfer layer, using a method involving high-density plasma chemical vapor deposition and hydrogen implantation to define a cleave plane, allowing for improved frequency isolation and reduced parasitic currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high resistivity handle wafers are used in SOI substrates, then device-to-device isolation and passive component Q-factors are improved, but parasitic surface conduction and non-linear distortion occur due to accumulation layers

Engineering Contradiction:

Improvedevice-to-device isolationVSAvoidparasitic surface conduction

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A trap-rich layer is introduced as an intermediary between the handle wafer and the buried oxide layer. This layer contains high densities of charge traps that capture and neutralize carriers before they can form accumulation layers at the handle wafer surface, thereby eliminating parasitic surface conduction while preserving the electrical isolation benefits of high resistivity handle wafers

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The electrical properties of the handle wafer interface are modified by changing the carrier concentration through the trap-rich layer. By controlling the trap density and depth profile in this layer, the carrier distribution is altered to prevent accumulation layer formation, thus resolving the parasitic conduction issue while maintaining high resistivity characteristics

Inventive Principle:

Principle #35Parameter changes

2Reliability

If high resistivity handle wafers are used in SOI substrates, then passive component Q-factors are improved, but non-linear distortion and device cross-talk are introduced

Engineering Contradiction:

Improvepassive component Q-factorsVSAvoidnon-linear distortion

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The trap-rich layer serves as a mediator that intercepts charge carriers in the handle wafer, preventing them from forming accumulation layers that cause non-linear distortion. By capturing these carriers, the layer eliminates the source of distortion while preserving the high Q-factor characteristics of passive components

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The potential harmful effect of carrier accumulation is converted into a beneficial trap-rich region. The carriers that would otherwise form harmful accumulation layers are instead captured and stored in the trap-rich layer, transforming a potential problem into a solution that improves RF signal integrity

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The substrate effectively reduces parasitic surface conduction and non-linear distortion, enhancing frequency isolation and operational speeds in RF devices by incorporating a trap-rich layer that manages carrier lifetime and mobility.

Implementation Method 1

silicon nitride layer positioned on the first side of the high-resistivity base layer; a silicon dioxide layer positioned on the silicon nitride layer

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 2

a trap-rich region including arsenic diffused within the first side of the high-resistivity base layer

Methodology Applied

Scientific EffectDiffusion: Diffusion

Implementation Method 3

a method involving high-density plasma chemical vapor deposition and hydrogen implantation to define a cleave plane

Methodology Applied

Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS11894261B2Silicon-on-insulator substrate including trap-rich layer and methods for making thereof

Publication Date: 2024.02.06 CROCKETT ADDISON

AI summary

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.