NAND Erase Voltage Control to Prevent Shared Bit Line Disturb
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Solution Overview
Problem
Erase disturb occurs in NAND memory cells when erasing one group of memory cells, affecting adjacent cells and leading to unintended changes in their threshold voltage, which can result in data loss and reduced memory performance.
Innovation Solution
Applying specific voltage control techniques to unselected memory cells during the erase process, including raising the channel potential of unselected memory cells to a voltage that prevents erasure and using a set of voltages that decrease from the bit lines to the memory cells to inhibit gate-induced drain leakage, thereby preventing erase disturb while keeping current consumption low.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase voltage is applied to bit lines to erase selected memory cells, then erasure of selected cells is achieved, but erase disturb occurs in unselected memory cells sharing the same bit lines
Solution Approach 1:
The patent applies preliminary anti-action by raising the channel potential of unselected memory cells to a voltage level (e.g., 10V) before applying the erase voltage to bit lines. This pre-established protective potential prevents the erase voltage from causing unintended erasure in unselected cells, thereby eliminating erase disturb while maintaining efficient erasure of selected cells
2Reliability
If channel potential of unselected memory cells is raised to prevent erase disturb, then data integrity is maintained, but additional voltage control complexity is introduced
Solution Approach 1:
The patent segments the memory structure into selected and unselected regions, applying different voltage potentials to each. By controlling the channel potential specifically in unselected memory cell regions through dedicated control lines, the system prevents erase disturb without requiring complex global voltage control, thus managing complexity through spatial segmentation
3Reliability
If multiple voltage levels are applied to different regions, then erase disturb is prevented, but power consumption increases
Solution Approach 1:
The patent applies local quality by raising the channel potential specifically in unselected memory cell regions rather than throughout the entire memory array. This localized voltage control prevents erase disturb only where needed, minimizing unnecessary power consumption in selected regions and other inactive areas, thus balancing reliability improvement with energy efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively prevents erase disturb in unselected memory cells during the erasing of selected memory cells, maintaining data integrity and reducing power consumption, thus enhancing the reliability and efficiency of NAND memory operations.
Implementation Method 1
using a set of voltages that decrease from the bit lines to the memory cells to inhibit gate-induced drain leakage
Data Source
AI summary
Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.