TFT Array Substrate Electrode Layout for Stable Parasitic Capacitance

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Solution Overview

Problem

In the field of display technology, the preparation of array substrates is often hindered by unstable processes and limited accuracy, leading to parasitic capacitors with varying capacitance values and decreased yield and quality of the array substrate.

Innovation Solution

The proposed solution involves an array substrate design where the first and second electrodes of the thin film transistor are configured such that their projections on the base do not overlap with the gate projection, allowing for increased average distance between the electrode ends, thus reducing the likelihood of short circuits and improving preparation accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the electrodes are positioned closer to the gate to reduce parasitic capacitance, then the parasitic capacitance decreases, but the risk of short circuits increases due to process instability

Engineering Contradiction:
Improvepreparation yieldVSAvoidalignment accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The electrode structure is divided into multiple segments: a first electrode body positioned over the gate, first ends extending from the bodies, and adjustment subparts connecting them. This segmentation allows the main electrode bodies to maintain proper alignment with the gate while the ends and adjustment subparts provide tolerance against misalignment, reducing short circuit risk without increasing parasitic capacitance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different parts of the electrode have different functional characteristics. The electrode bodies positioned over the gate maintain precise alignment for optimal capacitance control, while the ends extending beyond the gate projection and the adjustment subparts provide mechanical tolerance and connection flexibility. This local differentiation allows each region to optimize its function independently.

Inventive Principle:
Principle #3Local quality

2Reliability

If the electrode configuration is optimized to reduce parasitic capacitance, then the capacitance consistency improves, but the device complexity increases

Engineering Contradiction:
Improvecapacitance consistencyVSAvoidelectrode structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The electrode structure employs asymmetric configuration where the first ends extend in one direction from the electrode bodies, and adjustment subparts are positioned specifically to connect ends while providing alignment tolerance. This asymmetric design achieves capacitance consistency by controlling the critical electrode-body alignment while allowing flexibility in the connection regions, without requiring symmetric complexity throughout the entire structure.

Inventive Principle:
Principle #4Asymmetry

3Reliability

If the average distance from electrode ends to each other is increased, then the short circuit probability decreases, but the parasitic capacitance control becomes more difficult

Engineering Contradiction:
Improveshort circuit resistanceVSAvoidcapacitance control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The electrode structure utilizes three-dimensional positioning where electrode bodies are positioned over the gate in one dimension, while ends extend in another direction, and adjustment subparts provide vertical or lateral connection paths. This multi-dimensional arrangement allows increasing the distance between ends to reduce short circuit probability while maintaining precise capacitance control through the body-over-gate configuration in a different spatial dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12242161B2Array substrate and display panel
Publication Date: 2025.03.04 CHENGDU ZHONGDIAN PANDA DISPLAY TECH CO LTD
  • US12242161B2 patent drawing
  • US12242161B2 patent drawing
  • US12242161B2 patent drawing

AI summary

The present application provides an array substrate and a display panel. The array substrate includes a gate of a thin film transistor; a first electrode of the transistor, including a first body and a first end; a second electrode of the transistor, including a second body and a second end; orthographic projections of the first body and the second body being located in an orthographic projection of the gate, orthographic projections of at least partial area of the first end and at least partial area of the second end not overlapping with the orthographic projection of the gate, an orthographic projections of the first end and the second end being both located on the same side of the orthographic projection of the gate; in a first direction, an average distance from the first end to the second end is greater than that from the first body to the second body.