Segmented Strained SOI Substrates for pFET and nFET Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with fully depleted silicon-on-insulator (FD SOI) architecture face challenges in optimizing both p-type (pFETs) and n-type (nFETs) field effect transistors due to the difficulty in simultaneously achieving compressive and tensile strained regions on a shared substrate.
Innovation Solution
A semiconductor structure and method are developed to create both tensile-strained and compressive-strained regions on a common substrate by forming a tensile-strained silicon-on-insulator structure, reducing the tensile strain through ion implantation, and then recrystallizing and introducing germanium to achieve compressive strain in the pFET regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ion implantation is performed to reduce tensile strain, then compressive strain can be achieved for pFETs, but the active layer becomes amorphous requiring additional processing
Solution Approach 1:
Ion implantation is performed as a preliminary action to reduce the tensile strain in the active layer before germanium condensation. This preliminary strain reduction creates the necessary conditions for achieving compressive strain in pFET regions, even though it temporarily amorphizes the material. The subsequent thermal processing restores crystallinity and completes the strain transformation.
Solution Approach 2:
The amorphization of the active layer during ion implantation, which initially appears harmful, is converted into a benefit. The amorphous state facilitates subsequent germanium diffusion and condensation, enabling the transformation from tensile to compressive strain. The thermal annealing step then restores the crystalline structure, turning the temporary amorphization into a useful intermediate state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the simultaneous optimization of both pFETs and nFETs on a shared substrate, enhancing performance by achieving higher transconductance, cutoff frequency, and maximum frequency while reducing device leakage.
Implementation Method 1
implanting at least a portion of the active layer with ions to render at least a portion of the active layer amorphous and reduce the tensile strain
Implementation Method 2
thermally annealing the implanted at least a portion of the active layer and recrystallizing the at least a portion of the active layer previously rendered amorphous
Implementation Method 3
performing a germanium condensation process on the recrystallized at least a portion of the active layer to form a SiGe material having a compressive strain
Data Source
AI summary
A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.