Nanosheet Wafer Frontside-Backside Routing for Wiring Density
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Solution Overview
Problem
The complexity of integrated circuits is limited by the number of package terminations that can connect processors to other system components and the available space for wiring, which restricts the number of transistors and interconnections on a single chip.
Innovation Solution
A semiconductor device with both frontside and backside signal and power lines is developed, where the frontside includes signal lines transmitting to transistors and the backside includes power lines and signal lines, with vias extending through the chip to connect these lines, allowing for efficient signal transmission and power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If more transistors and interconnections are added to increase circuit complexity, then processing capability improves, but the available space for wiring and package terminations becomes insufficient
Solution Approach 1:
The patent utilizes both the front side and back side of the semiconductor substrate for wiring and interconnections. By extending vias through the entire substrate thickness and routing lines on both surfaces, the design effectively doubles the available wiring area, allowing increased circuit complexity without proportionally increasing the chip footprint.
2Adaptability or versatility
If more package terminations are added to increase connectivity, then system integration improves, but the number of available terminations becomes limited by physical constraints
Solution Approach 1:
The invention distributes package terminations across both the front and back sides of the substrate. This spatial distribution on two surfaces effectively doubles the termination capacity compared to single-sided designs, enabling higher connectivity without proportionally increasing the lateral dimensions of the package.
3Ease of manufacture
If signal lines and power lines are routed on the frontside only, then manufacturing is simpler, but space utilization is inefficient
Solution Approach 1:
The patent divides the wiring function into two segments: frontside routing for signal lines and backside routing for power lines. This segmentation allows efficient utilization of both substrate surfaces, with each side optimized for specific signal types, thereby improving overall space utilization while maintaining manufacturing feasibility through standardized multi-layer PCB techniques.
Data Source
AI summary
A semiconductor device includes an integrated circuit chip having a frontside and a backside. The frontside includes a frontside signal line configured to transmit signals to a first terminal of a transistor arranged in the integrated circuit chip, and the backside includes a backside power line configured to transmit power to a second terminal of the transistor. The semiconductor device further includes a contact configured to connect a gate of the transistor to a backside signal line configured to transmit signals to the gate of the transistor. The semiconductor device further includes a via extending through the frontside and the backside of the integrated circuit chip. The via is configured to transmit signals between a lowermost contact on the frontside and an uppermost contact on the backside of the integrated circuit chip.