3D Memory String Electrode Layout for Simpler NAND Integration
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Solution Overview
Problem
Conventional semiconductor memory devices with three-dimensional memory cells face challenges in achieving high integration and large capacity due to complex manufacturing processes, including high costs and increased complexity from the need for multiple photo etching processes and variations in transistor properties, which are exacerbated by the skewering dumpling structure of SGT transistors.
Innovation Solution
A nonvolatile semiconductor memory device with a plurality of memory strings, each comprising pillar-shaped semiconductors, insulation films, and electrodes, where the electrodes form conductor layers in a two-dimensional spread, allowing for reduced word line drivers and simplified manufacturing processes by using a common conductor layer per layer, thereby reducing chip area and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional memory cell with SGT transistor structure is used to achieve high integration, then the integration degree increases, but the manufacturing complexity and cost increase due to multiple photo etching processes and variations in transistor properties
Solution Approach 1:
The memory cell is divided into multiple layers with memory transistors stacked vertically. Each layer contains memory strings with pillar-shaped semiconductors surrounded by insulation films and electrodes. This segmentation allows parallel processing of multiple layers, reducing the number of sequential photo etching steps while maintaining high integration density.
Solution Approach 2:
The invention transitions from a planar two-dimensional memory cell layout to a three-dimensional stacked structure. Memory transistors are arranged in multiple vertical layers, with each layer containing memory strings composed of pillar-shaped semiconductors. This dimensional change increases storage capacity per chip area while simplifying the photo etching process by enabling simultaneous patterning of multiple layers.
2Manufacturing precision
If multiple photo etching processes are performed to manufacture three-dimensional memory cells, then the manufacturing precision can be maintained, but the manufacturing time and cost increase
Solution Approach 1:
Insulation films are formed around the pillar-shaped semiconductors before the final electrode patterning step. This preliminary formation of insulation structures allows subsequent electrodes to be patterned in a single photo etching process rather than requiring multiple sequential steps, reducing manufacturing time while maintaining precision through the protective insulation layer.
Solution Approach 2:
Multiple functional components (memory transistors, insulation films, electrodes) are combined into an integrated stacked structure where memory transistors from different layers are interconnected through shared bit lines and word lines. This merging allows simultaneous processing of multiple layers, reducing the total number of photo etching operations required while maintaining manufacturing precision through unified structure formation.
Data Source
AI summary
A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.