L-Shaped SONOS Memory Array Sidewall Structure
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Solution Overview
Problem
Existing methods for manufacturing sidewall SONOS memory devices are complex, time-consuming, and costly due to the sequential nature of forming memory array and peripheral transistors on the same die, leading to lower production rates and revenue.
Innovation Solution
A method involving the formation of gate stacks on both array and periphery regions of a substrate, followed by the deposition of dielectric materials and charge-storing layers, with subsequent etching to create L-shaped storage structures adjacent to the gate stacks, allowing for integrated and logic-compatible processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sequential manufacturing steps are used to form memory array and periphery transistors separately, then each region can be optimized independently, but the manufacturing process becomes complex and time-consuming
Solution Approach 1:
The patent combines the formation of memory array transistors and periphery transistors into a single integrated process flow. Multiple gate stacks are formed simultaneously using the same deposition and etching steps, eliminating the need for separate sequential processing. This merging of previously distinct manufacturing steps reduces process complexity while maintaining the ability to form different transistor types on the same die.
Solution Approach 2:
The patent employs universal process steps that can form both memory array transistors and periphery transistors. The same dielectric materials, deposition techniques, and etching processes are used for both regions, allowing a single manufacturing sequence to produce multiple transistor types with different functions. This multi-functionality approach simplifies the overall manufacturing process while maintaining region-specific optimization.
2Manufacturing precision
If sequential manufacturing steps are used for memory array and periphery, then each region receives dedicated processing, but production rate decreases
Solution Approach 1:
The patent implements continuous manufacturing where deposition and etching steps proceed without interruption across the entire wafer surface. Rather than completing all steps for one region before moving to another, the process continuously forms multiple gate stacks across array and periphery regions simultaneously. This continuity eliminates idle time and maintains high production rates while ensuring both regions receive adequate processing.
Solution Approach 2:
The patent performs preliminary formation of all gate stacks before subsequent processing steps. By establishing both memory array and periphery gate stacks in advance using the same initial steps, the patent enables parallel progression through remaining manufacturing stages. This preliminary action allows downstream processes to proceed simultaneously across different regions, increasing overall production efficiency.
3Manufacturing precision
If multiple sequential processing steps are implemented, then detailed transistor structures can be formed, but manufacturing time and cost increase
Solution Approach 1:
The patent segments the formation process into distinct modular stages: initial gate stack formation, charge trap layer deposition, and selective etching. Each segment performs a specific function and can be executed in a standardized sequence. This segmentation allows complex transistor structures to be built from simple, repeatable steps, reducing the overall manufacturing cycle time while maintaining structural detail through careful control of each segment.
Solution Approach 2:
The patent adds vertical dimensionality to the manufacturing process by forming multi-layer gate stacks with charge trap layers embedded within. Instead of creating complex structures through multiple lateral processing steps, the patent builds complexity in the vertical direction through stacked dielectric and conductive layers. This dimensional approach reduces the number of sequential processing steps required while achieving detailed transistor structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, enhancing production efficiency and revenue by integrating sidewall SONOS and peripheral structures in a single, streamlined process flow.
Implementation Method 1
Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed so that a first storage structure is formed adjacent to the first sidewall of the first gate stack
Implementation Method 2
A charge-storing material is formed over the first dielectric material
Implementation Method 3
A first dielectric material is formed over the substrate to cover the first gate stack and the second gate stack
Data Source
AI summary
Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.