3D NAND Word Line Capacitance Reduction via Segmented Switching
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Solution Overview
Problem
In 3D NAND flash memory devices, the stacked word lines exhibit high parasitic capacitance due to their planar structures, leading to increased RC delays, lower operating speeds, higher power consumption, and program disturb issues between neighboring blocks.
Innovation Solution
The implementation of linking elements with switches responsive to string select line signals, which connect word lines to patterned conductors and a word line decoder, allowing selective application of voltages to reduce coupling capacitance between stacks, thereby minimizing cross-talk during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar word line structures are used in stacked memory devices, then manufacturing is simplified and coverage of vertical channel structures is improved, but parasitic capacitance increases leading to higher RC delays and lower operating speeds
Solution Approach 1:
The patent divides the continuous planar word line structure into segmented word line segments within each block. By segmenting the word lines at block boundaries, the capacitance coupling between adjacent blocks is reduced while maintaining the planar structure benefits within each block. This allows simplified manufacturing within blocks while reducing parasitic effects.
Solution Approach 2:
The patent extracts and removes the word line structures from blocks that are not currently being accessed. By taking out inactive word lines from the operational circuit, the parasitic capacitance affecting active word lines is reduced, thereby improving operating speed without complicating the manufacturing of active blocks.
2Quantity of substance
If stacked planar word lines are used to increase storage capacity, then density is improved, but coupling capacitance between word lines in neighboring blocks increases causing program disturb
Solution Approach 1:
The memory device is divided into multiple independent blocks with word lines segmented between blocks. This segmentation creates electrical isolation between neighboring blocks, preventing program disturb from propagating to adjacent blocks while maintaining high storage capacity through vertical stacking within each block.
Solution Approach 2:
The patent introduces intermediate structures (such as isolation regions or dielectric layers) between word lines of neighboring blocks. These intermediary elements act as barriers that reduce coupling capacitance and prevent electrical interference between blocks, thereby improving reliability without sacrificing storage density.
3Device complexity
If continuous word line structures are applied across multiple blocks, then manufacturing complexity is reduced, but RC delays increase due to large parasitic capacitance
Solution Approach 1:
Word lines are segmented into block-specific segments rather than forming continuous structures across all blocks. This reduces the total capacitance of each word line segment, thereby reducing RC delays and signal propagation time while maintaining relatively simple manufacturing processes within each block.
Data Source
AI summary
A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips. The plurality of stacks of conductive strips includes a plurality of intermediate levels of conductive strips configured as word lines and an upper level of conductive strips configured as string select lines. A plurality of first patterned conductors is disposed above the plurality of stacks of conductive strips. A plurality of linking elements connects conductive strips in respective intermediate levels in the plurality of intermediate levels of conductive strips to first patterned conductors in the plurality of first patterned conductors. The linking elements in the plurality of linking elements include switches responsive to signals in conductive strips in the upper level of conductive strips.