3D NAND Memory Device Stacked Cell Array Layers
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Solution Overview
Problem
Conventional nonvolatile memory devices, particularly NAND-type, face limitations in updating speed and density due to their two-dimensional structure, which hinders their application in high-capacity and high-density storage solutions.
Innovation Solution
A three-dimensional NAND-type nonvolatile memory device is developed with multiple cell array layers stacked on a semiconductor substrate, featuring a common source line connected to strings of memory cells, allowing independent programming of layers and improved integration, along with a specific programming method that prevents unselected cells from being programmed using self-boosting and local self-boosting techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a two-dimensional NAND-type memory structure is used, then the device achieves high density through series-connected cell strings, but the update speed is limited and scalability is hindered
Solution Approach 1:
The patent transitions from a two-dimensional memory structure to a three-dimensional stacked structure by vertically stacking multiple cell array layers. Each layer contains memory cell strings connected in series, and the layers are stacked along the vertical direction. This dimensional change enables significantly increased memory density while maintaining the high-speed update capability through independent programming of each layer via separate common source lines.
2Quantity of substance
If multiple cell array layers are stacked to increase density, then the degree of integration improves, but independent programming capability and control complexity are compromised
Solution Approach 1:
The patent divides the stacked memory structure into multiple independently controllable cell array layers, each with its own common source line. This segmentation allows each layer to be programmed independently without affecting other layers, simplifying the control logic despite the increased number of layers. The segmentation approach enables scalable design where additional layers can be added without fundamentally changing the control architecture.
Solution Approach 2:
The patent implements a universal control architecture where the same programming circuitry and control logic can be applied to any number of stacked layers. Each layer uses identical cell string structures and programming mechanisms, allowing the system to handle multiple layers through repeated application of the same functional blocks, thereby reducing overall system complexity.
3Reliability
If conventional programming methods are used in stacked structures, then unselected cells cannot be accidentally programmed, but the programming precision and error prevention are insufficient
Solution Approach 1:
The patent applies local quality by implementing self-boosting and local self-boosting techniques that create highly localized voltage conditions during programming. The self-boosting mechanism raises the potential of selected string channels to programming levels, while local self-boosting further enhances the voltage at the specific memory cell location. These localized voltage enhancements ensure that only the targeted selected cells reach the programming threshold, while unselected cells remain below it, thereby preventing accidental programming with high precision.
Data Source
AI summary
Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of strings. Each of the plurality of strings has string and ground select transistors and a plurality of memory cells connected in series between the string and ground select transistors. A common source line is on each of the plurality of cell array layers. Each common source line is connected with first sides of the plurality of strings on a corresponding cell array layer. A plurality of bit lines is connected with second sides of the plurality of strings disposed on the cell array layers and arranged in the vertical direction to the semiconductor substrate. A plurality of word lines is connected with the plurality of memory cells.