3D Semiconductor Memory Double Channel Structure
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Solution Overview
Problem
As the number of stacked layers of memory cells in three-dimensional nonvolatile semiconductor memory devices increases, the channel resistance grows, leading to reduced current flow necessary for sensing the state stored in memory cells, hindering capacity expansion.
Innovation Solution
A semiconductor memory device with a double channel structure is implemented, comprising an inner channel semiconductor layer, an insulating interlayer, and an outer channel semiconductor layer, which enhances the ON current of memory cells by allowing increased stacking without significant resistance increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers of memory cells is increased to expand capacity, then memory capacity is improved, but channel resistance becomes larger and current flow is reduced
Solution Approach 1:
The channel layer is segmented into multiple independent channel layers (first channel layer, second channel layer, third channel layer) stacked in the thickness direction. Each channel layer provides separate current conduction paths, effectively dividing the total channel resistance into parallel paths. This segmentation allows the memory device to maintain low channel resistance even as the number of stacked memory cell layers increases, thereby preserving current flow capability while expanding memory capacity.
2Quantity of substance
If the number of stacked layers of memory cells is increased, then memory capacity is improved, but channel resistance becomes larger
Solution Approach 1:
Multiple channel layers are nested within a single memory hole structure, with each channel layer containing memory cells stacked in the thickness direction. The first, second, and third channel layers are vertically nested, allowing memory capacity to be increased by adding more stacked layers without significantly increasing the horizontal footprint or overall device complexity. The nested structure enables efficient use of vertical space while maintaining manageable device architecture.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.