3D Memory Cell Double Word Line for Lower Parasitic Capacitance
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in integration due to the need for expensive equipment for miniaturization, and there is a need for a more efficient way to increase memory cell density while reducing parasitic capacitance.
Innovation Solution
A three-dimensional semiconductor memory device is developed with a double word line structure comprising dual work function electrodes, where a low work function electrode is adjacent to the capacitor and a high work function electrode is adjacent to the bit line, allowing for vertical stacking of memory cells and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine pattern formation technology to increase integration, then memory cell density increases, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking architecture. Memory cells are stacked in the vertical direction (perpendicular to substrate) with bit lines extending vertically, enabling higher integration density without requiring further miniaturization of lateral patterns, thus avoiding the need for increasingly expensive fine pattern formation equipment
2Quantity of substance
If memory cell size is reduced to increase density, then integration increases, but parasitic capacitance increases
Solution Approach 1:
By stacking memory cells vertically in the third dimension, the patent achieves higher density while maintaining adequate spacing between cells in the lateral plane. This vertical arrangement reduces overlapping areas between adjacent memory cells and their associated electrodes, thereby reducing parasitic capacitance compared to lateral miniaturization approaches
Solution Approach 2:
The patent divides the memory cell structure into vertically stacked segments with isolated bit lines and word lines for each cell layer. This segmentation isolates the electrical fields of adjacent memory cells, reducing inter-cell parasitic capacitance and improving signal integrity
3Quantity of substance
If three-dimensional vertical stacking is implemented to increase density, then memory cell density increases, but device height increases
Solution Approach 1:
The patent employs thin film dielectric layers and conductive layers in the vertical stacking structure. By using highly integrated thin film technologies, the patent achieves high cell density while minimizing the vertical thickness of each memory cell layer, thereby controlling overall device height despite the increased number of stacked cells
Solution Approach 2:
The patent optimizes critical dimensions such as channel width, channel length, and dielectric layer thickness to achieve high integration density while controlling vertical footprint. By carefully adjusting these parameters, the patent balances density improvement against device height constraints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases memory cell density, improves leakage current by forming a low electric field, and reduces the height of the memory cell, enhancing integration and refresh characteristics while lowering power consumption.
Implementation Method 1
each of the dual work function electrodes includes a high work function electrode which is adjacent to the bit line; and a low work function electrode which is adjacent to the capacitor and having a lower work function than the high work function electrode
Data Source
AI summary
A semiconductor memory device includes: an active layer spaced apart from a substrate wherein the active layer extends in a direction parallel to the substrate, and includes a channel; a bit line extending in a direction perpendicular to the substrate and coupled to a first end of the active layer; a capacitor coupled to a second end of the active layer; and a double word line including a pair of dual work function electrodes that extend in a direction crossing the active layer with the active layer interposed therebetween, wherein each of the dual work function electrodes includes: a high work function electrode which is adjacent to the bit line; and a low work function electrode which is adjacent to the capacitor and having a lower work function than the high work function electrode.