3D Ferroelectric Memory Cell With Dual-Gate Threshold Control
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Solution Overview
Problem
Existing semiconductor memories, such as SRAM and DRAM, lose stored data when powered off, and FeRAMs, while non-volatile, do not efficiently utilize dual gate structures for enhanced voltage differentials.
Innovation Solution
A memory cell design featuring a vertical FET with dual gate electrodes and a ferroelectric memory film that allows for independent voltage application across each gate, enabling dual threshold voltages based on polarization direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If FeRAM uses a single gate structure, then the device complexity is reduced, but the voltage differential across the memory film is insufficient for optimal performance
Solution Approach 1:
The gate structure is segmented into two separate gate electrodes (first gate electrode and second gate electrode) positioned on opposite sides of the memory film. This segmentation allows independent voltage application to each gate, enabling the creation of a enhanced voltage differential across the memory film that exceeds what a single gate could provide, thereby resolving the contradiction between structural simplicity and voltage differential effectiveness.
Solution Approach 2:
The patent transitions from a single-dimensional gate control (one gate) to a two-dimensional gate arrangement (two gates on opposite sides of the memory film). This dimensional expansion allows voltages to be applied from both sides of the memory film simultaneously, creating a stronger and more uniform electric field across the entire memory film thickness, thus achieving higher voltage differential without excessive complexity.
2Power
If a dual gate structure is implemented, then the voltage differential across the memory film is enhanced, but the device complexity increases
Solution Approach 1:
The dual gate structure serves multiple functions: it creates enhanced voltage differential across the memory film, enables independent threshold voltage control through polarization direction, and allows for both read and write operations with optimized voltage signals. By making the gate structure multi-functional, the patent justifies the increased complexity with substantial performance benefits across multiple operational dimensions.
Solution Approach 2:
The patent utilizes parameter changes in the form of independent voltage applications to each gate electrode, allowing dynamic control of the electric field strength and direction across the memory film. This parameter control enables optimization of read/write operations and threshold voltage adjustment without requiring complex additional circuitry, thereby managing device complexity while maintaining high voltage differential effectiveness.
3Manufacturing precision
If the memory cell uses a larger area, then the manufacturing precision requirements are reduced, but the memory device footprint increases
Solution Approach 1:
The patent employs a vertical stacking architecture where the memory cell components (gate electrodes, memory film, source/drain regions) are arranged in three-dimensional space rather than purely planar layout. This vertical dimensionality allows the memory cell to achieve high integration density without proportionally increasing the planar footprint, effectively decoupling manufacturing precision requirements from device area.
Solution Approach 2:
The dual gate structure is nested around the memory film with source and drain regions positioned at opposite ends, creating a compact cross-sectional arrangement. This nested configuration maximizes the use of vertical space within the memory cell, allowing high-performance dual gate operation without requiring excessive lateral area, thus maintaining small footprint while achieving precise component alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances memory performance by allowing for more efficient data storage and retrieval with reduced footprint, improving read/write speed and reducing errors.
Implementation Method 1
a ferroelectric memory film that allows for independent voltage application across each gate, enabling dual threshold voltages based on polarization direction
Data Source
AI summary
In an embodiment, a device includes a first gate structure over a substrate, the first gate structure including a first gate electrode over a first side of a first gate dielectric; a first electrode and a second electrode disposed over a second side of the first gate dielectric opposite the first side; a second gate structure disposed between the first electrode and the second electrode, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric at least laterally surrounding the second gate electrode; and a semiconductor film disposed between the first electrode and the second electrode and at least laterally surrounding the second gate structure, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.