3D Memory Wiring Through Dummy Channels for Signal Integrity
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Solution Overview
Problem
Current 3D semiconductor memory devices face challenges in further improving integration density and performance while maintaining reduced size and preventing breakdown voltage reduction due to potential differences between common source lines and bit lines.
Innovation Solution
The implementation of a semiconductor memory device with a 3D structure, featuring a cell region over a substrate, a peripheral circuit region, main and dummy channel films, and an upper wiring structure, where dummy channel films electrically couple the upper wiring to the peripheral circuit region, reducing the length of routing paths and using materials with lower resistance to enhance signal integrity and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If routing paths are lengthened to connect peripheral circuit region to upper wiring structure, then device complexity is reduced, but signal integrity deteriorates and resistance increases
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by forming dummy channel films that extend vertically through the cell structure. This allows electrical connection between the peripheral circuit region and upper wiring structure through the vertical dimension, shortening the routing path while maintaining device complexity at acceptable levels.
Solution Approach 2:
The dummy channel films serve as intermediary conductive elements that facilitate electrical connection between the peripheral circuit region and upper wiring structure. These dummy channel films are specifically designed to provide low-resistance pathways, acting as mediators that improve signal integrity without requiring complex lateral routing.
2Productivity
If integration density is increased by adding more cell strings, then productivity improves, but breakdown voltage decreases due to potential differences
Solution Approach 1:
The dummy channel films are configured to equalize potential distribution across multiple cell strings by providing dedicated electrical connection paths. This equipotential design reduces potential differences between common source lines and bit lines, preventing breakdown voltage reduction even as integration density increases with additional cell strings.
Solution Approach 2:
The patent segments the electrical connection paths by providing separate dummy channel films for different cell strings. This segmentation allows independent potential control and equalization for each cell string, enabling higher integration density while maintaining adequate breakdown voltage characteristics through localized potential management.
Data Source
AI summary
A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.