3D Memory Cell Stacks With Dummy Source Contact Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity, particularly in transitioning from two-dimensional to three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor device design featuring a first and second stack structure with gate electrodes, a dummy structure, and channel structures, along with source contact structures and interconnection lines, optimized for efficient data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking by forming multiple stack structures (first stack structure, second stack structure, third stack structure) vertically aligned over the substrate. This vertical stacking enables increased data storage capacity by utilizing the third dimension (height) for memory cell arrangement, with each stack structure containing multiple memory cells connected through word lines and bit lines.
2Quantity of substance
If three-dimensional memory cell arrangement is implemented, then data storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the three-dimensional memory structure into multiple discrete stack structures (first stack structure, second stack structure, third stack structure), each containing memory cells connected through word lines and bit lines. This segmentation allows for modular fabrication and assembly, where each stack can be manufactured and characterized independently, thereby reducing the overall manufacturing precision requirements compared to a monolithic three-dimensional structure.
3Productivity
If gate electrodes are stacked in multiple directions, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent implements vertical stacking of gate electrodes in the third dimension (perpendicular to the substrate surface) to increase integration density. Multiple gate electrodes are stacked within each stack structure, with word lines extending vertically through the stack structures to connect memory cells. This three-dimensional gate arrangement enables higher integration density by utilizing vertical space for electrical connections.
Solution Approach 2:
The patent employs a nested structure where word lines are embedded within and extend through the stack structures, with bit lines positioned between adjacent stack structures. The gate electrodes are nested within the stack structures, and the word lines are nested within the dielectric layers. This nesting arrangement optimizes space utilization and increases integration density while maintaining manageable device complexity through systematic layering.
Data Source
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Figure 2B
AI summary
A semiconductor device includes a source structure (SS), first and second stack structures (ST1, ST2), including first gate electrodes (130A) stacked on the source structure (SS) to be spaced apart from each other; a dummy structure (DS) on the source structure (SS) between the first and the second stack structures (ST1, ST2), and including second gate electrodes (130B) stacked to be spaced apart from each other; first separation regions (MS1) passing through the first and second stack structures (ST1, ST2), and spaced apart from each other; second separation regions (MS2) extending between each of the first and second stack structures (ST1, ST2) and the dummy structure (DS); channel structures (CH) passing through the first and second stack structures (ST1, ST2), and respectively including a channel layer (140), connected to the source structure (SS) through the channel layer (140); and first source contact structures (180) passing through the dummy structure (DS), and respectively including a first contact layer (184) connected to the source structure (SS) through a lower surface of the first contact layer (184).