Read-Only Memories TRIZ Cases

By placing sensing circuits over memory cell pillars, this case improves nanoamp read-signal detection without sacrificing array density.

A read-path micropump stabilizes current between the sense transistor and global bitline to improve memory read accuracy despite threshold variation.

Fuse-bit comparison lets memory devices enable only revision-matched testmodes, avoiding BIOS or firmware updates across material versions.

Selective skipping of calibration data collection in NAND read-level calibration cuts latency, power use, and timeout risk once levels converge.

A one-pass shadow programming scheme for TLC and QLC NAND preserves read window budget and reliability without larger write buffers.

GIDL-based selective erase targets chosen NAND strings through selected data lines, reducing high-voltage stress, component damage, and energy use.

Grouping target states by coupling offsets cuts multi-level NAND program time while preserving read margin through staged verification.

Segmented 3D memory cell stacks use a dummy source-contact region to raise storage density, ease fabrication precision, and reduce noise.

A single verify read classifies memory-cell threshold voltage into three groups from cell current, cutting write time in nonvolatile memory.

Angled boron implantation deepens p-type regions in 3D NAND silicon columns, improving hole supply for faster body erase operations.

Using conductive features across multiple metallization layers, this capacitor structure boosts capacitance per area without relying on tighter lithography.

A conductive link between paired gates equalizes potential, reducing voltage drop and power consumption for steadier memory writes and reads.

A two-cell atomic flag lets non-volatile memory detect tearing during interrupted writes and preserve consistent flag states.

Batch ODT enable and selective disable commands cut NAND read communication delay while preserving precise timing control.

A DLL and delay line center DQS within DQ timing margins, reducing read/write errors on high-speed NAND flash buses.

By reading threshold distribution data with read data, the controller updates history offsets to cut I/O load, latency, and error correction time.

Saved-register write recovery lets shared flash memory suspend one write, run another, then resume quickly without changing flash bank design.

Read-count-aware page selection lets a memory controller write NAND pages more safely, improving usable space while protecting data retention.

Ferroelectric capacitive synapses store neural weights by voltage-controlled capacitance, cutting continuous current demand in dense neural networks.

Shared retention voltage and switch control cut SRAM leakage while improving retention stability and recovery across memory banks.

Applying an assistance voltage to a pass word line during GIDL erase cuts memory erase time while maintaining stable erasure.

By comparing cell counts before and after programming, this 3D NAND control approach detects severe program disturbance and supports reliable reads.

Downward floating-gate protrusions enlarge the channel interface, easing charge injection in scaled flash cells and widening the read window.

An isolated floating body and state-selective impact ionization reduce random dopant fluctuation effects and stabilize memory cell charge states.

A control block redirects and supplements internal power when wordline current demand rises, stabilizing vertical flash program and read operations.

Biasing the bottom select line before erase keeps adjacent flash blocks at consistent voltages, improving read-window margin during erase cycles.

Combining MRAM and ROM in one chip with shared peripheral control reduces circuit count, power use, and memory access overhead.

A reliability-based delay is inserted between two programming passes to protect weaker memory cells from program disturb without slowing all writes.

Pre-programming a defective memory deck with a voltage pattern limits program disturb and preserves usable half-good blocks.

Staged bottom-gate and common-source precharge improves NAND flash voltage ramping, cutting programming time and interference.

Sector information generates upper column address bits in advance, cutting command transmission cycles and improving semiconductor interface speed.

Alternating positive and negative weight cells share ADCs and cancel currents, cutting analog computing array area and power use.

Phased erase scheduling across NAND super blocks keeps host write throughput steady while avoiding large buffer memory.

Separate sensing nodes, pass transistors, and capacitive stabilization reduce charge sharing during data dumping and protect memory data reliability.

A time-varying single voltage pulse pre-conditions QLC cells to tighten threshold distribution, improving read margins and cutting program time.

Switch circuits float drive-transistor gates and apply boosted erase voltage for GIDL erase with less circuit area and lower breakdown risk.

Disconnecting unprogrammed wordlines during voltage ramp-up cuts read bit errors in partial NAND blocks without padding or extra regulators.

A verify step during erase resume checks cell state after pre-program suspension, cutting wait time and limiting overprogramming.

Semi-soft bit data is derived from strobe reads and adjacent cell states to cut corrective read latency while improving memory read accuracy.

A tensile-strained silicon channel boosts hot carrier generation in split-gate memory cells, cutting program-erase power and time.

Page type-specific bin selection lets a memory controller tune read thresholds to cut bit errors and improve data integrity.

Open bit count guides wear leveling in rewritable non-volatile memory, reducing tunneling oxide damage and extending SLC service life.

Preprogramming selected and neighboring word lines reduces lateral and vertical degradation, improving NAND memory data retention and reliability.

A five-port eFuse cell with two identical GAA NMOS transistors avoids substrate bias and bit-line voltage drop for more reliable programming.

A memory controller separates read disturb from retention charge loss to refresh only when needed, reducing wear, overhead, and wasted cycles.

Separate memory arrays and shared sensing circuitry increase storage capacity while limiting chip area growth in stacked semiconductor memory.

Standardized refresh registers let a host tune timing, partitions, and algorithms to protect flash data retention with less performance loss.

Non-volatile memory synapses enable in-situ vector-matrix computation, cutting synapse area and energy use in analog-digital neural arrays.

An integrated reference voltage circuit inside the page buffer removes external high-voltage generation, cutting area and memory circuit complexity.

Using multiple programmable elements in each PUF memory cell makes stored bit states harder to detect, improving resistance to cloning and tampering.