3D Memory Deck Voltage Control for Disturbance Suppression
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Solution Overview
Problem
As the number of stacked layers in three-dimensional memory devices increases, program voltage disturbance and pass voltage disturbance become larger during program erase read operations, affecting the reliability and efficiency of memory operations.
Innovation Solution
A memory device with multiple stacked memory decks, where each deck has memory cell layers and word line layers, and dummy memory cell layers and word line layers at junction positions, with a peripheral circuit that applies specific pass voltages to manage disturbances by maintaining higher voltages for selected memory decks and lower voltages for unselected decks, and using a soft cut voltage to form a potential barrier for residual electrons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers is increased to improve storage capacity, then the storage capacity is improved, but the program voltage disturbance and pass voltage disturbance become larger
Solution Approach 1:
The memory device is divided into multiple independent memory decks (first memory deck, second memory deck) stacked vertically. Each memory deck contains complete memory cell layers and word line layers that can be independently controlled. This segmentation allows separate voltage application to each deck, enabling independent program and read operations that prevent voltage disturbance from propagating across all layers.
Solution Approach 2:
Different voltage levels are applied to different memory decks based on their operational state. The selected memory deck receives higher pass voltage (first pass voltage) during program operations, while unselected memory decks receive lower pass voltage (second pass voltage). This local differentiation of voltage quality reduces overall voltage disturbance while maintaining necessary operating conditions for active memory regions.
2Quantity of substance
If the channel length becomes longer to accommodate more stacked layers, then the storage capacity is improved, but the program voltage disturbance and pass voltage disturbance become larger
Solution Approach 1:
The long channel is divided into multiple shorter channel segments, each belonging to a separate memory deck. This segmentation breaks the continuous long channel into manageable sections that can be independently voltage-controlled, reducing the cumulative voltage disturbance effect along the channel while maintaining the ability to access all memory cells.
Solution Approach 2:
Dummy memory cell layers are introduced at the junction positions between memory decks as intermediary structures. These dummy layers act as voltage transition zones that help isolate the electrical characteristics of adjacent memory decks, preventing voltage disturbance from propagating across deck boundaries and improving overall operational reliability.
3Reliability
If higher pass voltage is applied to unselected memory decks to maintain boosting potential, then the program voltage disturbance is reduced, but the pass voltage disturbance in unselected memory decks increases
Solution Approach 1:
The patent applies different pass voltage levels to different memory decks based on their selection state. Selected memory decks receive higher pass voltage to maintain boosting potential and suppress program voltage disturbance, while unselected memory decks receive lower pass voltage to minimize pass voltage disturbance. This localized voltage differentiation resolves the contradiction by applying high voltage only where necessary.
Solution Approach 2:
The patent preemptively applies lower pass voltage to unselected memory decks before program operations commence, preventing pass voltage disturbance from occurring in the first place. This preliminary anti-action approach avoids the need to later counteract voltage disturbance effects, thereby maintaining reliability in unselected regions while preserving boosting potential in selected regions.
Data Source
AI summary
A memory device includes a memory cell array having stacked first and second memory decks; and a peripheral circuit coupled to the memory cell array and configured to: when performing a program operation on a selected memory cell layer in the first memory deck, apply a voltage to a word line layer corresponding to the selected memory cell layer and apply a first voltage to a word line layer corresponding to an unselected memory cell layer in the first memory deck; apply a second voltage to the word line layer corresponding to the plurality of memory cell layers in the second memory deck; and apply a third voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck. The first voltage exceeds the second voltage, which exceeds the third voltage.