Memory Device Retry Mechanism for Program/Erase Verification
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Solution Overview
Problem
Flash memory devices lack a mechanism to confirm the success of program/erase operations, leading to potential memory cell failure and wear-out, which is only detected when read data does not match written data.
Innovation Solution
A memory device with a status register, interface control circuit, and write control logic that performs retry operations on a memory array, counting re-program/re-erase attempts and comparing this count to a threshold to determine the success of program/erase operations and assess memory cell wear-out.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If repeatedly programming and erasing the same memory cell, then the memory device can be re-used, but reading speed becomes slower and the memory cell may fail
Solution Approach 1:
The patent implements a feedback mechanism by introducing a result bit in the status register that provides real-time information about the success or failure of program/erase operations. This allows the system to detect wear-out conditions and memory cell failures promptly, enabling preventive measures to be taken before complete failure occurs, thus resolving the contradiction between re-usability and reliability
Solution Approach 2:
The patent performs preliminary detection of program/erase operation results immediately after each operation through the result bit status indication. By detecting wear-out conditions and failures in advance rather than waiting for read errors, the system can take preventive actions such as switching to spare blocks or reducing write operations, thereby extending the usable life of the memory device while maintaining reliability
2Device complexity
If no confirmation mechanism is provided for program/erase operations, then the device structure remains simple, but undetected failures lead to data corruption
Solution Approach 1:
The patent adds a minimal feedback mechanism through the result bit in the status register that indicates whether program/erase operations completed successfully. This simple one-bit status flag provides immediate confirmation of operation success without requiring complex verification protocols, thus improving data integrity while maintaining structural simplicity
Solution Approach 2:
The memory device performs self-verification of program/erase operations through the internal result bit status indication. The device automatically detects and reports operation failures without requiring external verification mechanisms, thereby ensuring data integrity while avoiding the complexity of external confirmation systems
Data Source
AI summary
A memory device is provided and includes a status register, a memory array, a memory controller, an interface control circuit, and a write control logic circuit. The status register stores a plurality of status bits and a first threshold. The interface control circuit is controlled by the memory controller to perform a data program/erase operation on the memory array and re-program/re-erase the memory array in a retry mode when the data program/erase operation is not complete. The write control logic circuit counts the number of times the memory array is re-programmed/re-erased in the retry mode to generate a retry counting value, compares the retry counting value with the first threshold to generate a result signal. The status register updates a result bit included in the status bits according to the result signal. The memory controller determines whether the data program/erase operation is successful according to the result bit.