Flash Memory Erase Sequencing for Adjacent Block Voltage Consistency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The inconsistent voltage ramping up of word lines in adjacent memory blocks due to parasitic capacitance in flash memory systems leads to reduced read-window margin and voltage distribution spacing sum, causing inefficiencies in erase operations.
Innovation Solution
Applying a bias voltage to the bottom select line of unselected memory blocks to turn on their transistors, followed by an erase operation with a controlled voltage sequence to manage parasitic capacitance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase operation is performed on first memory block, then erase efficiency is improved, but voltage inconsistency in adjacent memory blocks occurs due to parasitic capacitance
Solution Approach 1:
The method applies a bias voltage to the bottom select line of the second memory block before performing the erase operation on the first memory block. This preliminary action turns on the bottom select transistor of the adjacent memory block in advance, ensuring that the voltage ramps up consistently along with the source line during the subsequent erase operation, thereby preventing voltage inconsistency caused by parasitic capacitance.
Solution Approach 2:
The bias voltage applied to the bottom select line of the second memory block serves as a preliminary counter-action to the harmful effect of parasitic capacitance. By pre-turning on the bottom select transistor, the method counteracts the voltage ramping delay that would otherwise occur in adjacent memory blocks during the erase operation, maintaining voltage consistency across memory blocks.
2Stability of the object's composition
If bias voltage is applied to bottom select line of second memory block, then voltage consistency is improved, but device complexity increases
Solution Approach 1:
The method merges the control of the bottom select line with the existing erase operation timing. The bias voltage is applied during the same time period when the erase operation is being performed on the first memory block, and the bottom select line is set to floating state during the erase operation. This integrated approach maintains voltage consistency without requiring separate complex control circuits.
Solution Approach 2:
The bottom select line of the second memory block is set to a floating state during the erase operation, allowing its voltage to ramp up automatically along with the source line voltage. This self-service mechanism eliminates the need for additional active control during the erase operation, reducing control complexity while maintaining voltage consistency.
3Object-affected harmful factors
If bottom select line is set to floating state during erase operation, then parasitic capacitance effect is reduced, but voltage control precision becomes challenging
Solution Approach 1:
The method changes the voltage state of the bottom select line from an active driven state to a floating state during the erase operation. This parameter change allows the voltage to ramp up naturally with the source line, reducing the harmful parasitic capacitance effect. The bias voltage applied beforehand ensures that the floating state starts from an appropriate voltage level, maintaining control precision.
Solution Approach 2:
By applying the bias voltage to the bottom select line before setting it to floating state, the method ensures that the voltage starts from a known and controlled level. This preliminary action guarantees that when the line is floated, the voltage ramps up consistently with the source line, maintaining voltage control precision while reducing parasitic capacitance effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces voltage differences between word lines and channels, maintaining consistent voltage levels and enhancing the read-window margin and voltage distribution during erase cycles.
Implementation Method 1
the bottom select transistor of the second memory block may be turned on by coupling a source line voltage to a word line of the second memory block through a parasitic capacitance of the bottom select transistor
Data Source
AI summary
According to one aspect of the present disclosure, a method of operating a memory is provided. The method may include applying a bias voltage to a bottom select line of a second memory block of the memory during a first time period to turn on the bottom select transistor of the second memory block. The memory may include a first memory block and the second memory block, and the bottom select transistor is coupled to a bottom select line. The method may include performing a first erase operation during a second time period after the first time period by providing an erase operating voltage to a source line of the first memory block, and setting the bottom select line of the second memory block to a floating state.