Flash Memory Correction Unit Bypasses Broken Bitlines
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Solution Overview
Problem
In flash memory devices, broken bitlines during erase verification lead to repeated verification failures, as the system continues to attempt verification on defective lines until timeout, causing inefficiencies in the erase process.
Innovation Solution
A semiconductor device with a correction unit for erase verification, featuring grounding switches connected between bitlines and a page buffer, which grounds broken bitlines during erase verification, allowing the system to bypass faulty lines and prevent verification failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the verification procedure continues to verify broken bitlines until timeout, then the verification process is thorough, but the erase verification time is excessively long and productivity is reduced
Solution Approach 1:
The patent applies preliminary action by pre-identifying and recording the addresses of broken bitlines before the erase verification operation. The correction unit stores this information in advance, so when verification is needed, the system can immediately bypass known defective lines without performing unnecessary verification steps, thus resolving the contradiction between thoroughness and speed
Solution Approach 2:
The patent extracts the problematic verification steps for broken bitlines by separating them from the normal verification flow. The correction unit identifies and removes (bypasses) the verification operations on known defective lines, allowing the verification process to focus only on functional lines, thereby improving productivity without compromising reliability
2Reliability
If the verification procedure attempts to verify all bitlines including broken ones, then the verification is complete, but repeated verification failures occur causing time loss
Solution Approach 1:
The patent introduces an intermediary component - the correction unit - that sits between the verification system and the broken bitlines. This correction unit uses stored address information to intercept and bypass verification attempts on defective lines, preventing repeated verification failures while maintaining complete verification of functional lines, thus eliminating time loss without compromising completeness
3Reliability
If grounding switches are connected to all bitlines, then broken bitlines can be bypassed, but the device complexity increases
Solution Approach 1:
The patent applies local quality by making the grounding switches selective rather than universal. Each grounding switch is specifically associated with a particular bitline address that has been identified as broken. This localized approach ensures that grounding switches are only activated for defective lines when needed, bypassing them without affecting the normal operation of functional lines, thus managing device complexity efficiently
Data Source
AI summary
A semiconductor device and a method for accelerating erase verification process thereof are introduced, in which a correction unit of erase verification is connected between broken bit lines of the semiconductor device and a page buffer. Grounding switches in the correction unit of erase verification are allowed to connect the broken bit lines to ground during an erase verification process by means of a specific circuit arrangement with respect to the broken lines. Thereby, the earth voltage is received, and further, that the broken bit lines pass the erase verification is identified by the page buffer, further saving time consumed in repeated verifications in the conventional technology significantly.