Page Buffer Circuit Optimizing Memory Read Time
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Solution Overview
Problem
The increasing complexity of memory devices due to multi-functionality and high integration leads to decreased read performance due to prolonged valley search operations in threshold voltage distributions, which increase read time.
Innovation Solution
A memory device with a page buffer circuit featuring multiple stages of page buffer units performing different sensing operations, a counting circuit to count memory cells in distinct threshold voltage regions, and a control circuit to determine development time periods based on these counts, optimizing the valley search operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If valley search operation is performed on threshold voltage distribution to improve read reliability, then read reliability is improved, but read time is increased and read performance is decreased
Solution Approach 1:
The page buffer units are divided into multiple stages, with each stage performing a specific sensing operation. The first stage performs a first sensing operation and the second stage performs a second sensing operation, allowing parallel processing of different threshold voltage regions. This segmentation enables the valley search operation to be conducted more efficiently by distributing the counting tasks across multiple stages rather than sequentially.
Solution Approach 2:
The first page buffer units perform a first sensing operation to count memory cells in a first threshold voltage region, and the second page buffer units perform a second sensing operation to count memory cells in a second threshold voltage region. These preliminary counting actions are performed in parallel before the final read operation, allowing the valley search to be optimized in advance and reducing the overall read time.
2Productivity
If multiple page buffer units perform different sensing operations in parallel, then counting operations are accelerated, but device complexity increases
Solution Approach 1:
The page buffer units are designed with multi-functionality, where each unit can perform different sensing operations depending on its stage. The same basic page buffer structure is reused across multiple stages, with each stage configured to perform a specific sensing operation. This universal design allows parallel processing of multiple threshold voltage regions while avoiding the need for completely separate circuitry for each function, thereby managing complexity.
Solution Approach 2:
Different sensing operations are performed by changing parameters such as the threshold voltage levels and sensing signals applied to different stages of page buffer units. The first page buffer units use a first sensing signal while the second page buffer units use a second sensing signal, allowing parallel counting in different threshold voltage regions without requiring fundamentally different circuit architectures.
Data Source
AI summary
A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.