Embedded SRAM Retention Voltage Sharing for Faster Mode Recovery
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Solution Overview
Problem
Existing memory devices face challenges in optimizing retention and recovery times due to variations in diode retention circuits, leading to inefficiencies in power consumption and data retention, particularly in static random access memory (SRAM) applications.
Innovation Solution
The embedded memory device incorporates a retention voltage supply circuit and array voltage supply circuits with shared retention and power switches, utilizing metal RC delay for optimized mode transitions and diode drain voltage sharing between sub-arrays or banks, reducing leakage current and diode variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diode retention circuit is used in SRAM to improve data retention and reduce power consumption, then data stability is improved, but variations in retention circuit performance occur due to diode parameter variations
Solution Approach 1:
The patent merges multiple diode retention circuits into a shared retention circuit that serves multiple SRAM banks. By combining the retention functions of multiple individual diodes into a single shared circuit, the design reduces the number of discrete diode components and minimizes the impact of individual diode parameter variations on overall system performance.
Solution Approach 2:
The shared retention circuit is designed to serve multiple SRAM banks simultaneously, providing universal retention functionality across different memory blocks. This multi-functional approach allows a single retention circuit to support various banks, reducing the need for bank-specific retention circuits and thereby minimizing performance variations.
2Productivity
If retention time and recovery time are optimized for different memory sizes generated by a memory compiler, then operational efficiency is improved, but the complexity of controlling mode transitions increases
Solution Approach 1:
The patent implements dynamic control of retention and recovery times based on the actual memory size and operational requirements. The mode transition control is designed to adaptively adjust timing parameters according to the specific memory configuration, allowing optimal performance across different memory sizes while managing complexity through structured control logic.
Solution Approach 2:
The system changes operational parameters (retention time, recovery time, mode transition timing) based on memory size and operational state. By dynamically adjusting these parameters rather than using fixed values, the design achieves optimal efficiency for different memory configurations without requiring completely separate control circuits for each size.
3Loss of energy
If leakage current is minimized through voltage sharing in retention mode, then power consumption is reduced, but the time required for mode transitions increases
Solution Approach 1:
The patent prepares voltage transition paths and control signals in advance to facilitate rapid mode transitions. By pre-configuring the circuit paths and control logic before mode changes are needed, the system can quickly switch between retention and operational modes while minimizing the time required for voltage adjustments and reducing the impact on overall transition speed.
Data Source
AI summary
An embedded memory device includes a retention voltage supply circuit outputting a retention voltage in response to a retention activation signal, and a plurality of array voltage supply circuits outputting corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits respectively include an array switch providing the retention voltage as a corresponding array voltage in response to the retention activation signal, a power switch providing a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and an auxiliary circuit compensating the corresponding array voltage during a write operation or a read operation.