Differential Non-Volatile Memory Cell for In-Memory Neural Network Computation
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Solution Overview
Problem
Artificial neural networks are computationally intensive and require significant memory and data transfer operations, particularly in loading and transferring weights between layers, which can be energy inefficient and complex.
Innovation Solution
The use of Binary Neural Networks (BNNs) with weights stored in differential resistive non-volatile memory cells, allowing for in-memory computation through voltage divider mechanisms, enabling concurrent multiplication and accumulation operations within a memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional memory and processing units are used separately, then data transfer operations can be performed, but energy consumption increases and computational complexity increases
Solution Approach 1:
The patent merges memory storage and computational processing into a single integrated system. Non-volatile memory cells perform both data storage and multiply-accumulate operations by utilizing voltage divider mechanisms directly within the memory array, eliminating the need for separate data transfer between memory and processing units.
Solution Approach 2:
The patent introduces control circuits as intermediary components that enable the memory cells to perform computational functions. These control circuits apply voltage patterns to selected word line pairs and sense output voltages, mediating between the stored weights and the computational operations without requiring external processing units.
2Reliability
If weights are stored in traditional memory, then data can be retained, but data transfer operations become intensive and complex
Solution Approach 1:
The patent combines data retention and computational functionality into the same memory structure. Non-volatile memory cells store weights while simultaneously enabling in-memory computation through voltage divider mechanisms, eliminating the need for data transfer to external processing units.
Solution Approach 2:
The patent segments the computational function into the memory array itself. Each memory cell pair is configured to independently perform multiply-accumulate operations on stored weights, distributing the computational workload across the memory structure rather than concentrating it in a separate processing unit.
3Measurement precision
If more memory cells are used to store weights, then neural network accuracy improves, but memory requirements and device complexity increase
Solution Approach 1:
The patent makes memory cells multi-functional by enabling them to both store weights and perform computational operations. Each non-volatile memory cell pair serves dual purposes: retaining weight values and participating in multiply-accumulate operations, thereby reducing the need for additional dedicated processing components.
Solution Approach 2:
The patent transitions computation from a separate processing dimension to the memory dimension. By utilizing voltage divider mechanisms within the memory array, the system performs computation in the same physical dimension where data is stored, eliminating the need for additional processing hardware.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces computational complexity and memory requirements, enhancing energy efficiency and parallel processing capabilities for neural network operations.
Implementation Method 1
differential resistive non-volatile memory cells
Implementation Method 2
in-memory computation through voltage divider mechanisms
Data Source
AI summary
Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.