3D Floating Gate Structure for Scaled Flash Memory Programming
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Solution Overview
Problem
As flash memory cells scale down, short channel effects lead to performance degradation due to difficulty in driving charge carriers into the floating gate, resulting in inefficient data programming and smaller read windows.
Innovation Solution
The flash memory structure incorporates a floating gate with protrusions extending outward from its lower surface, increasing the interfacing area with the channel region, facilitating easier charge carrier injection and enhancing data programming efficiency and read window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory cells are scaled down, then device density is improved, but short channel effects cause performance degradation due to difficulty in driving charge carriers into the floating gate
Solution Approach 1:
The floating gate is designed with protrusions that extend vertically downward into the substrate, transitioning from a planar two-dimensional structure to a three-dimensional structure. This dimensional change increases the interfacing area between the floating gate and channel region, enabling sufficient charge carrier injection capability even in scaled-down devices, thus resolving the contradiction between device density improvement and data programming efficiency maintenance
2Productivity
If floating gate interfacing area with channel region is increased, then charge carrier injection efficiency is improved, but device area increases
Solution Approach 1:
The floating gate structure introduces localized protrusions at specific positions where charge carrier injection is needed, rather than uniformly increasing the entire floating gate area. This local quality enhancement concentrates the interfacing area increase at critical regions, improving charge carrier injection efficiency while minimizing the overall area increase of the floating gate structure
3Ease of manufacture
If conventional floating gate structure is used, then manufacturing simplicity is maintained, but read window becomes smaller due to short channel effects
Solution Approach 1:
The floating gate is segmented into a main body portion and multiple protrusion portions that extend into the substrate. This segmentation allows the protrusions to be formed through selective etching and deposition processes in existing fabrication lines, maintaining manufacturing simplicity while the increased interfacing area from the segmented structure improves the read window by enhancing charge carrier injection efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced floating gate design improves data programming efficiency and read window by increasing the interfacing area, making it easier for charge carriers to enter the floating gate, thus improving overall device performance.
Implementation Method 1
a floating gate disposed over the substrate between the select gate and the source region
Data Source
AI summary
The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.