3D Multilayer Capacitor Structure for Higher Capacitance Density
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Solution Overview
Problem
Existing capacitor structures in semiconductor devices face challenges in increasing capacitance per area without compromising device performance and scalability, particularly in NAND flash memory, due to limitations in lithographic critical dimensions, dielectric material suitability, and inefficient use of space in multi-layer layouts.
Innovation Solution
A layered capacitor structure is formed using conductive structures across multiple metallization layers, with a conformal dielectric layer and a conductive fill structure, leveraging three-dimensional surfaces of interconnect structures to enhance capacitance, and utilizing a dedicated dielectric to optimize MIM capacitor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar capacitor structures are used, then manufacturing process is simple, but capacitance per area is limited
Solution Approach 1:
The patent transitions from traditional planar capacitor structures to three-dimensional capacitor structures that utilize multiple metallization layers. Conductive structures are formed across multiple layers (e.g., first metallization layer, second metallization layer, third metallization layer) with dielectric materials filling the spaces between them, creating vertical stacking that dramatically increases capacitance per area by utilizing the third dimension for charge storage.
Solution Approach 2:
The capacitor structure employs nested conductive structures where conductive elements are placed within dielectric materials, and dielectric materials are placed between conductive structures across multiple layers. The conductive fill structures are nested within the dielectric material voids, creating a compact multi-layer nested arrangement that maximizes space utilization for capacitance.
2Quantity of substance
If multi-layer capacitor structures are implemented, then capacitance per area increases, but manufacturing precision requirements increase
Solution Approach 1:
The capacitor structure is segmented into discrete conductive structures and dielectric regions across multiple metallization layers. Each layer contains specific conductive elements (e.g., first conductive structures, second conductive structures, third conductive structures) that are independently formed and then electrically connected through vertical interconnects, allowing standardized manufacturing processes to be applied to each segment.
Solution Approach 2:
The dielectric materials serve multiple functions: they provide electrical insulation between conductive structures of opposite polarity, enable vertical stacking across multiple layers, and fill spaces between conductive elements to create uniform capacitor regions. This multi-functionality simplifies manufacturing by combining several requirements into a single material and process step.
3Reliability
If conventional dielectric materials are used, then manufacturing is easier, but capacitor performance is suboptimal
Solution Approach 1:
The patent specifies particular dielectric material properties including dielectric constant values (e.g., first dielectric material with first dielectric constant, second dielectric material with second dielectric constant) and thickness parameters. By optimizing these parameters, the capacitor achieves enhanced performance in terms of charge storage capacity and voltage tolerance while maintaining compatibility with existing manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases capacitance per area, addressing the challenge of storage density while maintaining device efficiency and scalability, compatible with current manufacturing techniques and accommodating higher voltage operations.
Implementation Method 1
Capacitor structure using surfaces of three dimensional structures formed across multiple metallization layers
Data Source
AI summary
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a layered structure. The layered structure includes a first set of conductive structures that are horizontally formed in a first metallization layer, a second set of conductive structures that are horizontally formed in a second metallization layer, and a set of interconnect structures that is vertically formed and electrically couples the first set of conductive structures and the second set of conductive structures. The layered structure further includes conformal dielectric layer over surfaces of the first set of conductive structures, surfaces of the second set of conductive structures, and surfaces the set of interconnect structures. The layered structure further includes a conductive fill structure that surrounds the conformal dielectric layer.