NAND Flash Memory Intermediate Level Programming

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Solution Overview

Problem

Existing multilevel programming techniques in NAND flash memory devices face issues with program disturb, where threshold voltages of already programmed memory cells shift due to parasitic capacitance coupling, leading to increased row-bit error rates and degraded programming performance.

Innovation Solution

Implementing a method where memory cells are programmed to an intermediate level from the lowest data state using a blanket voltage, allowing subsequent programming to higher levels without verifying threshold voltages, thereby reducing charge-storage-structure-to-charge-storage-structure interference and narrowing threshold-voltage ranges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If single-pass programming methods are used to program memory cells to multiple levels, then programming speed is improved, but threshold-voltage range width increases leading to program disturb and higher error rates

Engineering Contradiction:

Improveprogramming speedVSAvoidthreshold-voltage range width

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The programming process is divided into multiple passes, where each pass programs memory cells to a specific target level. The first pass programs cells to an intermediate level, and subsequent passes program cells to their final target levels. This segmentation allows for better control of threshold-voltage distribution and reduces program disturb effects.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Memory cells are preliminarily programmed to an intermediate level in the first pass before being programmed to their final target levels in subsequent passes. This preliminary action establishes a foundation that narrows the threshold-voltage range and reduces interference during final programming operations.

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If memory cells are programmed directly to higher levels without intermediate steps, then programming time is reduced, but charge-storage-structure-to-charge-storage-structure interference increases

Engineering Contradiction:

Improveprogramming timeVSAvoidcharge-storage-structure-to-charge-storage-structure interference

Core Design Contradiction:

Loss of timeVSObject-generated harmful factors

Solution Approach 1:

The direct programming path from lowest level to higher levels is segmented into multiple programming passes. Each pass targets a specific level, reducing the voltage swing and charge injection per pass, thereby minimizing interference between adjacent charge storage structures.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The programming process uses periodic action by applying programming pulses in multiple passes with verification steps in between. This periodic approach allows the system to reset and re-target memory cells, reducing cumulative interference effects that would occur with continuous direct programming.

Inventive Principle:

Principle #19Periodic action

3Measurement precision

If verification steps are performed after each programming operation, then programming accuracy is improved, but programming time increases significantly

Engineering Contradiction:

Improveprogramming accuracyVSAvoidprogramming throughput

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

Verification is performed selectively rather than universally. The system determines whether verification is needed based on the programming state and target levels, performing verification only when necessary to maintain accuracy while avoiding unnecessary verification steps that would reduce throughput.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

Different verification strategies are applied to different memory cells based on their programming status and target levels. Cells that have been successfully programmed to the correct level skip verification, while cells that need verification receive it. This local differentiation maintains accuracy for critical cells while preserving throughput for the overall array.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the width of threshold-voltage ranges for higher levels by about 20-30% compared to single-pass programming methods, improving reliability without significantly increasing programming time.

Implementation Method 1

programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena

Methodology Applied

Scientific EffectCharge storage: Capacitance

Implementation Method 2

threshold voltages of already programmed memory cells shift due to parasitic capacitance coupling

Methodology Applied

Scientific EffectParasitic capacitance coupling: Parasitic Capacitance

Data Source

PatentUS10504600B2Apparatus configured to program memory cells using an intermediate level for multiple data states

Publication Date: 2019.12.10 MICRON TECHNOLOGY INC

AI summary

Apparatus including an array of memory cells and a controller configured to program all memory cells of a grouping of memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level, and to respectively program all the memory cells of the grouping of memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.