Page Buffer Circuit Layout to Prevent Sensing Node Charge Sharing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Charge sharing occurs between a parasitic capacitor and a sensing node during the discharging period of a data dumping operation in page buffer circuits, leading to undesired voltage drops and potential data processing errors.
Innovation Solution
Implementing a page buffer circuit with a multi-stage structure where page buffer units and cache latches are isolated, using pass transistors to connect sensing nodes in common, and incorporating capacitors to stabilize voltage levels and prevent charge sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If page buffer units and cache latches share common sensing nodes, then device complexity is reduced and integration is improved, but charge sharing occurs between parasitic capacitors and sensing nodes causing voltage drops and data errors
Solution Approach 1:
The patent divides the sensing node into separate sensing nodes for page buffer units and cache latches, eliminating the shared sensing node that causes charge sharing. Each page buffer unit has its own sensing node connected to its main latch, while cache latches share a common sensing node only among themselves, preventing charge sharing between page buffer units and cache latches.
Solution Approach 2:
The patent introduces separate sensing nodes as intermediaries between page buffer units and cache latches. Instead of direct sharing, the sensing nodes act as isolated interfaces that prevent harmful charge sharing while still enabling necessary data transfer and sensing operations.
2Ease of manufacture
If transistors are connected directly to form latches, then manufacturing simplicity is maintained, but parasitic capacitance causes charge sharing and voltage fluctuations during data dumping
Solution Approach 1:
The patent extracts and separates the sensing node from the transistor junctions. By placing sensing nodes at distinct locations away from transistor junctions, the parasitic capacitance that causes charge sharing is eliminated. The sensing nodes are extracted from the direct transistor connection path to prevent harmful capacitive coupling.
Solution Approach 2:
The patent converts the potentially harmful parasitic capacitance at transistor junctions into beneficial design guidance. By recognizing where parasitic capacitance naturally occurs, the design places sensing nodes away from these junctions, transforming the harmful effect into a design rule that improves reliability.
3Productivity
If sensing nodes are discharged during data dumping, then data transfer speed is improved, but charge sharing with parasitic capacitors causes voltage drops and processing errors
Solution Approach 1:
The patent segments the discharge path by providing separate sensing nodes for page buffer units and cache latches. During data dumping, each sensing node can be discharged independently through its own path, preventing charge sharing with parasitic capacitors while maintaining fast data transfer speeds.
Solution Approach 2:
The patent performs preliminary isolation of sensing nodes from parasitic capacitors by separate node design before the discharge operation begins. This preliminary structural separation ensures that when discharge occurs, charge sharing cannot happen, protecting data accuracy while enabling rapid discharge for high-speed transfer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents voltage fluctuations and maintains stable data processing by reducing charge sharing, ensuring reliable data transfer and improved timing characteristics in memory devices.
Implementation Method 1
a parasitic capacitor corresponding to a parasitic capacitance caused by a junction of the first transistor and the second transistor is connected between the first transistor and the second transistor
Data Source
AI summary
An example page buffer circuit includes a plurality of page buffer circuits and a plurality of cache latches connected with the plurality of page buffer circuits through a combined sensing node. Each of the plurality of page buffer circuits includes a main latch connected with a corresponding sensing node. The main latch includes a first transistor connected with a corresponding sensing node and configured to be driven by a monitoring signal, a first latch circuit configured to latch data, and a second transistor connected with the first transistor and configured to be driven by a voltage level of a node latching data in the first latch circuit, and a parasitic capacitor corresponding to a parasitic capacitance caused by a junction of the first transistor and the second transistor is connected between the first transistor and the second transistor.