Memory Peripheral Switch Circuit for GIDL Erase Voltage Control
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Solution Overview
Problem
Existing memory devices face challenges in efficiently performing gate-induced-drain-leakage (GIDL) erase operations due to the generation of gate-induced-drain-leakage (GIDL) during erase operations, which can lead to increased circuit area and reliability issues.
Innovation Solution
A memory system with a peripheral circuit that includes switch circuits to control drive transistors, allowing for controlled voltage application to float the control terminals and provide a threshold-voltage-exceeding voltage to assist in GIDL erase operations, reducing the need for large low dropout regulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large low dropout regulators are used to provide voltages for GIDL erase operations, then voltage supply capability is improved, but circuit area increases
Solution Approach 1:
The patent extracts the voltage boosting function from large low dropout regulators and implements it using compact voltage boosting circuits that can generate higher voltages (e.g., 20V-30V) from lower supply voltages, thereby reducing the area required for voltage generation while maintaining the necessary voltage supply capability for GIDL erase operations
Solution Approach 2:
The patent changes the voltage parameters by using voltage boosting circuits that dynamically generate higher voltages during erase operations. The voltage boosting circuits can generate voltages significantly higher than the supply voltage (e.g., boosting 12V to 20V-30V), allowing the system to achieve the required voltage levels without using large area regulators
2Power
If high voltages are applied to drive transistors during erase operations, then GIDL erase capability is improved, but transistor breakdown risk increases
Solution Approach 1:
The patent applies preliminary action by using voltage boosting circuits that generate the required high voltages (20V-30V) before the erase operation begins. The boosted voltages are stored in capacitors and then applied in a controlled manner to the bit lines and source lines, ensuring that the drive transistors receive the necessary voltage levels without experiencing uncontrolled voltage spikes that could cause breakdown
Solution Approach 2:
The patent introduces voltage boosting circuits as intermediary components between the supply voltage and the memory strings. These circuits act as mediators that convert lower supply voltages to the higher voltages needed for GIDL erase operations, while also providing controlled voltage delivery that prevents direct application of excessive voltages to the drive transistors, thereby reducing breakdown risk
3Device complexity
If simple voltage generation circuits are used, then device complexity is reduced, but voltage control precision deteriorates
Solution Approach 1:
The patent employs dynamic voltage boosting circuits that can adjust their operation based on the specific erase requirements. The voltage boosting circuits dynamically generate voltages during erase operations, providing precise voltage control when needed while remaining inactive during other operations, thus balancing complexity and precision by making the advanced voltage generation capability conditional rather than always active
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the efficiency and reliability of GIDL erase operations by minimizing circuit area and preventing transistor breakdown, thereby improving the overall performance of the memory system.
Implementation Method 1
erase voltages are provided to both ends of the memory string in the memory block through the drive transistor, such that the top select gate (TSG) and bottom select gate (BSG) of the memory string may generate gate-induced-drain-leakage (GIDL), so as to perform a GIDL erase on the memory string
Data Source
AI summary
The present disclosure discloses a memory device, comprising a plurality of memory blocks each comprising a plurality of memory strings connected between a common source line and a plurality of bit lines and a peripheral circuit, the peripheral circuit comprises a plurality of drive transistors, each drive transistor connected between the common source line and a corresponding bit line of the plurality of bit lines; a first switch circuit connected between a first node and control terminals of the plurality of drive transistors; and a second switch circuit connected between the first node and the common source line.