Analog Weight Computing Array With Shared ADCs for Negative Weights
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Solution Overview
Problem
Existing analog computing units for artificial neural networks require separate ADCs for positive and negative weights, leading to increased size and power consumption due to the need for multiple bit lines and ADCs, which are area and energy-intensive.
Innovation Solution
Analog computing unit design with alternately arranged columns for positive and negative weight storage, sharing word lines and bit lines to cancel currents, reducing the need for half the number of ADCs by integrating them into every two rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate ADCs are used for positive and negative weights, then computing accuracy is maintained, but device size and power consumption increase
Solution Approach 1:
The patent combines the functionality of separate ADCs for positive and negative weights into a shared ADC resource. By alternating between reading positive weight columns and negative weight columns, the system merges what were previously separate conversion functions into a single ADC, reducing device area while maintaining computing accuracy through sequential processing
Solution Approach 2:
The patent implements periodic action by alternating between reading columns for positive weights and columns for negative weights in successive time periods. This time-division multiplexing approach allows a single ADC to serve both functions sequentially, reducing hardware requirements while maintaining the accuracy needed for both positive and negative weight computations
2Measurement precision
If separate ADCs are used for positive and negative weights, then computing accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent merges separate ADC functions into a single shared ADC, directly reducing the number of power-consuming components. By consolidating the analog-to-digital conversion functionality for both positive and negative weights into one ADC, the system reduces overall power consumption while maintaining computing accuracy through time-division multiplexing
Solution Approach 2:
The periodic alternation between processing positive and negative weight columns allows a single ADC to handle both functions over time, eliminating the need for two continuously operating ADCs. This reduces power consumption significantly while maintaining accuracy, as the ADC operates at full capacity during its allocated time periods rather than having two ADCs operating simultaneously at lower utilization
3Quantity of substance
If multiple bit lines are used for positive and negative weights, then weight storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent makes bit lines universal by enabling them to serve dual functions: storing positive weights during one time period and negative weights during another time period. This multi-functionality approach allows the same physical bit lines to be reused for different weight types, reducing the total number of bit lines needed while maintaining full weight storage capacity
Solution Approach 2:
The system uses periodic action to alternate the function of bit lines between storing positive weights and storing negative weights. By time-division multiplexing the bit lines, the patent reduces hardware complexity while maintaining the ability to store both positive and negative weights, as each bit line serves both purposes in succession rather than requiring dedicated lines for each weight type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces the size and power consumption of the computing unit by integrating ADCs for positive and negative weights, cutting the ADC count by half and optimizing layout area.
Implementation Method 1
analog computing unit for analog computing in a computing accelerator for implementing an artificial intelligence network
Implementation Method 2
multiplication and accumulation computations (MACs) are performed
Implementation Method 3
analog signals are converted into digital signals via the ADCs
Implementation Method 4
currents flowing from the plus cells and the minus cells arranged along the rows are canceled as much as corresponding values
Data Source
AI summary
An object is to provide a new analog computing unit capable of reducing the size of an analog computing unit and reducing the amount of power consumption by reducing use of analog-to-digital converters (ADCs) to ¼ as compared to prior arts. In an analog computing unit according to one embodiment, a flash memory cell array included in the unit has the structure in which unlike the prior arts, WLs and CGs are connected in a row direction, and EGs and RLs/BLs are connected in a column direction. Accordingly, the array has the structure in which even-numbered cells for negative weights in a column and odd-numbered cells for positive weights in the column form pairs in a read NN mode, or odd-numbered cells for negative weights in a column and even-numbered cells for positive weights in the column form pairs in a read mode.