NAND String Erase Using GIDL for Selected Data Lines
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Solution Overview
Problem
Conventional NAND flash memory erase operations require high voltage levels, which can lead to inefficiencies and potential damage to the electrical components.
Innovation Solution
The proposed method includes applying an independent erase operation by electrically floating the access lines corresponding to the erase voltage levels, which can lead to inefficiencies and potential damage to the electrical components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage levels are applied to erase memory cells, then erase operation can be completed, but electrical components may be damaged and energy consumption increases
Solution Approach 1:
The patent divides the memory block into multiple sub-blocks, each with independent select gates. This allows erase operations to be performed on specific sub-blocks independently using lower voltage levels, avoiding the need to apply high voltage to all memory cells simultaneously. The segmentation enables targeted erasure while protecting other components from voltage-induced damage.
Solution Approach 2:
The patent applies different voltage levels to different regions of the memory array. Specifically, high voltage is applied only to the channel regions of selected sub-blocks that require erasure, while other regions operate at normal voltage levels. This localized voltage application achieves effective erasure where needed while minimizing stress and potential damage to the overall electrical system.
2Reliability
If high voltage levels are applied to erase memory cells, then erase operation can be completed, but energy consumption increases
Solution Approach 1:
By segmenting the memory block into multiple sub-blocks with independent select gates, the patent enables erasure of only the necessary portions of memory. This reduces the total energy consumption compared to erasing entire blocks at high voltage, as energy is applied only where needed rather than uniformly across all memory cells.
Solution Approach 2:
The patent implements partial erasure actions by selectively erasing only specific sub-blocks or regions that require it, rather than performing full-block erasure. This partial action approach reduces unnecessary energy expenditure on already-erased or non-critical memory regions while maintaining erase reliability where required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method includes applying an independent erase operation by electrically floating the erase lines corresponding to the erase voltage levels, which can lead to inefficiencies and potential damage to the electrical components.
Implementation Method 1
generating gate-induced drain leakage (GIDL) in the channel structures of the selected data line
Data Source
AI summary
Memories might include a controller configured to cause the memory to apply a first voltage level to each data line of a plurality of data lines, generate gate-induced drain leakage (GIDL) from a selected data line to a channel structure of a respective string of series-connected memory cells, inhibit generation of GIDL from an unselected data line to a channel structure of a respective string of series-connected memory, and apply a second voltage level to a selected access line connected to a respective memory cell of each of the strings of series-connected memory cells, wherein the second voltage level is configured to remove charge from its respective memory cell of the respective string of series-connected memory cells of the selected data line and is configured to inhibit removal of charge from its respective memory cell of the respective string of series-connected memory cells of the unselected data line.