Column Address Generation Using Sector Bits for Faster Command Cycles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor apparatuses face challenges in quickly transmitting control signals between an external device and the semiconductor apparatus during fewer clock cycles to improve interface performance.
Innovation Solution
A column address generation circuit that includes a command set conversion section to generate column address information based on sector information and output a second command set, and a column address output section to output a fixed value as part of the column address, simplifying the conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional column address generation methods are used, then the interface performance between external device and semiconductor apparatus is limited, but the transmission time for control signals cannot be reduced to fewer clock cycles
Solution Approach 1:
The column address generation is divided into two parts: upper bits generated from sector information and lower bits generated from row address. This segmentation allows parallel generation of address parts and reduces the total time required for column address generation, enabling control signal transmission in fewer clock cycles and improving interface performance.
Solution Approach 2:
The upper bits of the column address are generated in advance from the sector information before the row address is fully processed. This preliminary action allows the column address generation to overlap with other operations, reducing the critical path delay and enabling faster control signal transmission between the external device and semiconductor apparatus.
2Measurement precision
If full column address information is transmitted during selection period, then address accuracy is maintained, but the transmission time exceeds the available clock cycles
Solution Approach 1:
The column address is segmented into upper bits (from sector information) and lower bits (from row address). The upper bits are transmitted during the setup period before selection, while the lower bits are transmitted during the selection period. This segmentation allows the complete column address to be transmitted within the available clock cycles while maintaining full address accuracy.
Solution Approach 2:
The upper bits of the column address are transmitted in advance during the setup period before the selection period begins. This preliminary transmission of part of the address information reduces the time required during the selection period, allowing the complete address to be transmitted within the available clock cycles without compromising accuracy.
3Loss of time
If sector information is used to generate column address, then transmission time is reduced, but the complexity of address generation logic increases
Solution Approach 1:
The address generation logic is segmented into two independent parts: upper bit generation from sector information and lower bit generation from row address. This segmentation simplifies each individual logic block while maintaining the overall functionality, reducing the complexity burden on any single component and enabling faster operation.
Solution Approach 2:
The sector information is used for multiple purposes: it identifies the selected sector and simultaneously generates the upper bits of the column address. This multi-functionality reduces the need for separate address generation logic, simplifying the overall system while enabling faster command set transmission.
Data Source
AI summary
A column address generation circuit including: a command set conversion section configured to generate column address information on the basis of sector information included in a first command set synchronized with a first clock signal, and to output a second command set from the first command set by replacing information on column address cycles of the first clock signal with the column address information in response to a conversion signal; and a column address output section configured to output a column address on the basis of the second command set.