DRAM Row Address Code Selection for Substandard Cell Refresh
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Solution Overview
Problem
Volatile memory cells in DRAMs lose data due to varying charge retention characteristics, requiring different refresh periods, leading to inefficient power consumption or complex circuitry when trying to account for these differences.
Innovation Solution
Grouping memory blocks with substandard cells for frequent refreshing and those without for less frequent refreshing, using a first and second refresh period respectively, to minimize power consumption and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory cells are refreshed with the same short period to accommodate cells with poorest charge retention, then data loss is prevented, but power consumption increases inefficiently
Solution Approach 1:
The patent segments memory blocks into different groups based on charge retention characteristics. Memory blocks are divided into first plurality (with substandard cells), second plurality (without substandard cells), and third plurality (without substandard cells). Each group is refreshed with different periods tailored to their specific retention needs, preventing uniform over-refreshing and reducing overall power consumption while maintaining data reliability.
2Use of energy by moving object
If different refresh timing is used for different memory cells to account for varying charge retention, then power consumption is optimized, but circuit complexity increases
Solution Approach 1:
The patent merges memory blocks with similar refresh requirements into common refresh groups. Memory blocks are combined into first, second, and third pluralities based on their charge retention characteristics. This merging approach allows multiple blocks to share the same refresh timing, significantly reducing circuit complexity compared to individual block control, while still optimizing power consumption through differentiated group-based refresh periods.
3Device complexity
If refresh operations are performed on all memory blocks simultaneously, then circuit complexity is reduced, but power consumption increases due to frequent refreshing of all blocks
Solution Approach 1:
The patent segments refresh operations into distinct phases corresponding to different memory block groups. The refresh controller performs refresh operations on the first plurality of memory blocks with a first refresh period, on the second plurality with a second refresh period, and on the third plurality with a third refresh period. This segmented approach allows simultaneous refreshing within each group while differentiating between groups, reducing overall power consumption compared to refreshing all blocks simultaneously at the shortest period.
Data Source
AI summary
A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.