Page Buffer Latch Segmentation for Memory Read Noise Reduction
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Solution Overview
Problem
Memory devices experience reliability issues due to power noise generated during read operations, which can lead to errors in sensing operations, primarily caused by the large current consumption of memory cells coupled to a single word line.
Innovation Solution
Incorporating page buffers with latches that perform bit line precharge operations and store results of sensing operations, where the value in the second latch is inverted when the first and second sensing operations yield different results, and using target threshold voltages for each sensing operation to manage current flow effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a sensing operation is performed on a plurality of memory cells coupled to a single word line at the same time, then the read operation efficiency is improved, but a large amount of current is consumed which generates noise on internal power voltage or internal ground voltage
Solution Approach 1:
The sensing operation is divided into multiple segments: a first sensing operation and a second sensing operation performed at different times. This segmentation reduces the simultaneous current consumption of memory cells, thereby reducing power noise on internal power and ground voltages while still enabling efficient read operations through sequential sensing of multiple memory cells coupled to the same word line.
Solution Approach 2:
The patent employs periodic sensing operations where memory cells are sensed in alternating time periods rather than all at once. The first sensing operation targets a first set of memory cells, followed by a second sensing operation for a second set of memory cells, creating a periodic pattern that distributes current consumption over time and reduces peak noise levels.
2Quantity of substance
If a large amount of current is consumed during the sensing operation, then more memory cells can be sensed simultaneously, but noise on internal power voltage or internal ground voltage increases which results in errors in the sensing operation
Solution Approach 1:
The population of memory cells is segmented into different groups that are sensed at different times. The first sensing operation senses a first group of memory cells, and the second sensing operation senses a second group of memory cells. This segmentation allows a large total number of memory cells to be sensed while maintaining reliability by limiting the current consumption and noise generation during each individual sensing operation.
Solution Approach 2:
The patent performs a first sensing operation before the second sensing operation, using the results from the first operation to inform or prepare for the second operation. This preliminary action allows the system to manage current consumption and noise exposure systematically, ensuring that each sensing operation benefits from the controlled conditions established by previous operations.
3Loss of information
If multiple sensing operations are performed on memory cells, then more comprehensive data can be obtained, but the complexity of the read operation increases
Solution Approach 1:
The page buffer structure is designed to perform multiple functions: it stores data from the first sensing operation, manages the second sensing operation, and handles data inversion logic all within a single integrated unit. This multi-functionality allows comprehensive data collection from multiple sensing operations without proportionally increasing overall system complexity, as the same hardware resources are reused across different operational phases.
Solution Approach 2:
The page buffer automatically performs data inversion when needed, based on the results of sensing operations. This self-service capability eliminates the need for external control logic to manually invert data, simplifying the overall read operation complexity while ensuring data completeness is maintained through automatic correction of sensing results.
Data Source
AI summary
A memory device includes a plurality of memory cells, bit lines connected to the plurality of memory cells, and page buffers coupled to the plurality of memory cells through the bit lines, and performing a read operation on the plurality of memory cells, wherein each of the page buffers comprises: a first latch controlling a bit line precharge operation during the read operation; and a second latch storing a result of a first sensing operation and a result of a second sensing operation performed after the first sensing operation, wherein a value stored in the second latch is inverted when the result of the first sensing operation and the result of second sensing operation are different from each other during the second sensing operation.