Unified MRAM and ROM Memory Layout With Shared Peripheral Control
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Solution Overview
Problem
Conventional computing systems require separate memory devices for fixed and variable codes, leading to increased system complexity and cost due to the need for multiple peripheral circuits for each memory type, and existing non-volatile memories lack integration with magnetoresistive random-access memory (MRAM) for efficient data storage.
Innovation Solution
A unified memory architecture integrating MRAM, flash, ROM, and optionally OTP memory types into a single device using a shared peripheral circuit, leveraging MRAM fabrication processes to form different memory types through magnetic and via masks, allowing for efficient data storage and access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate memory devices are used for fixed codes (ROM) and variable codes (flash memory), then data storage functionality is achieved, but system complexity increases due to multiple peripheral circuits
Solution Approach 1:
The patent merges ROM and flash memory into a single memory device with a unified architecture. Multiple memory types (ROM, flash memory, and optionally OTP memory) are integrated into one device, sharing common peripheral circuits including control logic, address decoding, and data I/O interfaces. This consolidation eliminates the need for separate peripheral circuits for each memory type, directly reducing system complexity while maintaining versatility through support for multiple memory types within the unified device.
Solution Approach 2:
The unified memory device implements multi-functionality by incorporating different memory types (ROM for fixed codes, flash memory for variable codes, and optionally OTP memory) that can be selectively accessed. The device provides universal memory access through a single interface, allowing the CPU to read both fixed and variable codes without requiring separate memory devices or multiple peripheral circuit sets, thereby reducing overall system complexity.
2Device complexity
If multiple separate memory devices are used, then different memory types can be accessed, but cost increases due to multiple peripheral circuits for each memory type
Solution Approach 1:
The patent combines multiple memory types (ROM, flash memory, and optionally OTP memory) into a single device that shares common peripheral circuits. The control logic, address decoding, and data I/O interfaces are unified across all memory types, eliminating redundant peripheral circuits that would exist if separate memory devices were used. This merging approach directly reduces the number of peripheral circuits while preserving the ability to access different memory types through the shared interface.
3Speed
If conventional memory architectures are used, then data storage is achieved, but read/write speed is limited due to separate memory device structures
Solution Approach 1:
The unified memory architecture merges multiple memory types into a single device with shared peripheral circuits and common data pathways. This consolidation eliminates the need for data to traverse separate interface circuits for each memory type, reducing access latency and improving read/write speed. The unified control logic can efficiently manage access to different memory types without the overhead of multiple separate control units, directly enhancing operational speed.
4Use of energy by moving object
If separate memory devices are used, then data storage functionality is provided, but power consumption increases due to multiple peripheral circuits operating simultaneously
Solution Approach 1:
The patent merges multiple memory types into a single device that shares common peripheral circuits. When accessing any memory type (ROM, flash memory, or OTP memory), only the necessary peripheral circuits are activated, rather than having multiple sets of peripheral circuits operating simultaneously as would be required with separate memory devices. This shared architecture directly reduces overall power consumption by eliminating redundant circuit operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces system complexity and cost by using a single peripheral circuit for multiple memory types, enhancing read/write speed and power efficiency while ensuring data security and immunities to external interference.
Implementation Method 1
Magnetoresistive random-access memory (MRAM) is a type of non-volatile random-access memory which stores data in magnetic domains. In particular, a MRAM device stores data in magnetic storage elements where the resistance of the magnetic storage elements changes as a function of the magnetic state.
Data Source
AI summary
A semiconductor memory device is formed on a semiconductor substrate including a first memory region, a second memory region and a logic region. A flash memory array is formed in the first memory region and includes an array of magnetoresistive random-access (MRAM) memory cells, each MRAM memory cell including an access transistor coupled to a magnetic tunnel junction (MTJ) storage element. A read-only (ROM) memory array is formed in the second memory region and includes an array of read-only (ROM) memory cells, each ROM memory cell including an access transistor coupled to a short or open circuit as the ROM storage element. A memory peripheral circuit is formed in the logic region. The memory peripheral circuit includes control circuits for receiving input commands and executing memory operations to the memory cells in the flash memory array and the read-only memory array.