Refresh Control Circuit Synchronizes Memory Rank Timing
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Solution Overview
Problem
In fault-tolerant computer systems, synchronizing the refresh timing of multiple memory ranks is challenging, leading to performance degradation due to differences in counter values and asynchronous resets, which can result in delayed data response and lockstep operation failures.
Innovation Solution
A refresh control circuit that initializes a counter using a synchronous reset signal at predetermined intervals, allowing for high-speed refresh when a synchronous reset signal is active, ensuring synchronized refresh timing across multiple memory ranks and minimizing performance degradation by intensively performing refresh only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If asynchronous reset signal is used to initialize the refresh counter, then the counter can be reset independently, but the refresh timing becomes unsynchronized across multiple memory ranks
Solution Approach 1:
A synchronous reset signal is introduced as an intermediary mechanism to initialize refresh counters across multiple memory ranks simultaneously. This synchronous reset signal acts as a mediator that coordinates the reset operation across all memory controllers, ensuring that all counters start from the same initial state at the same time, thereby achieving synchronized refresh timing while maintaining independent counter control capability.
2Reliability
If refresh is performed at maximum frequency to ensure memory reliability, then data retention is improved, but normal memory access performance degrades
Solution Approach 1:
The refresh interval is made dynamic by switching between two modes: a first interval for normal operation and a second (shorter) interval when synchronous reset is detected. This dynamic adjustment allows the system to perform intensive refresh only when necessary (during synchronization events), while maintaining normal access performance during steady-state operation. The refresh control circuit monitors the synchronous reset signal and automatically adjusts the refresh frequency accordingly.
Solution Approach 2:
The invention implements periodic intensive refresh at specific synchronization points (when synchronous reset signal is active) rather than continuous maximum-frequency refresh. By concentrating refresh operations at these periodic synchronization moments, the system ensures memory reliability is maintained while minimizing interference with normal memory access during other time periods.
3Adaptability or versatility
If refresh timing is not synchronized across multiple memory ranks, then each rank can operate independently, but lockstep operation fails and data response is delayed
Solution Approach 1:
The memory system is segmented into multiple independent ranks, each with its own refresh counter that can be independently controlled. The segmentation allows each rank to operate autonomously while the synchronous reset signal provides a coordination mechanism that aligns their operations. This segmented architecture with centralized synchronization enables both independent operation capability and synchronized lockstep execution.
Data Source
AI summary
Rank numbers specified by a second counter are refreshed in sequence by using a count value of a first counter which is initialized by a synchronous reset signal and counts timing for performing refresh, and the rank numbers specified by a refresh rank control unit are continuously refreshed in sequence in the case where the synchronous reset signal is active.