Memory Controller Scheduling for Phased NAND Super Block Erase
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Solution Overview
Problem
The inconsistency in write performance of NAND dies due to simultaneous erase operations leading to zero throughput during block erasure in storage devices, which affects overall host write throughput.
Innovation Solution
Implementing a memory controller that manages NAND dies in super blocks, completing program and erase operations in multiple steps and alternating them to minimize overlap, ensuring efficient data storage without significant buffer memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all NAND dies are managed with blocks being erased simultaneously, then erase operation completeness is improved, but host write throughput drops to zero during erase sections
Solution Approach 1:
The patent segments the erase operation into multiple phased steps (first phase erase, second phase erase, etc.) across different super blocks. Instead of erasing all blocks simultaneously, the controller performs partial erases in sequence, allowing programming operations to interleave with erase operations on different super blocks, thereby maintaining non-zero throughput while completing all erase operations.
Solution Approach 2:
The patent implements periodic alternation between programming and erase operations across different super blocks. The controller cycles through programming certain super blocks while erasing others, then switches phases periodically. This periodic action ensures that erase operations are completed systematically while programming operations continue on other blocks, preventing throughput from dropping to zero.
2Productivity
If buffer memory capacity is increased to maintain throughput during erase, then host write throughput consistency is improved, but device complexity and cost increase
Solution Approach 1:
The patent dynamically adjusts the scheduling of programming and erase operations based on the state of different super blocks. The controller monitors which super blocks are ready for programming versus which require erasing, and adaptively switches between operations to maintain continuous throughput. This dynamic scheduling eliminates the need for large static buffer memory allocations.
Solution Approach 2:
The patent ensures continuous useful action by guaranteeing that while some super blocks are being erased, other super blocks are being programmed. The phased approach maintains an invariant that at least one programming operation is always active alongside erase operations, ensuring continuous data flow and eliminating throughput gaps without requiring additional buffer memory.
Data Source
AI summary
A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.