Blocking State Memory Circuit for Secure CAM
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Solution Overview
Problem
Existing Content Addressable Memory (CAM) technologies lack a blocking state, which limits their ability to enhance security and efficiency in high-speed data comparison and authentication processes, particularly in applications like cryptography and network routers.
Innovation Solution
The introduction of a memory circuit with blocking states, utilizing two non-volatile transistors connected in series, allows for additional states such as 'no care' and 'blocking' states, enabling enhanced security and efficiency by configuring the memory cell to be in a blocking mode unless specific states match, thereby increasing impedance for mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional CAM architectures (BCAM/TCAM) are used, then data comparison speed is high, but security against unauthorized access and pattern extraction attacks is insufficient
Solution Approach 1:
The patent introduces a blocking state as an additional parameter state in the memory cell, transforming the traditional binary or ternary states into a quaternary state system (0, 1, BX, BB). This parameter change enables the memory cell to differentiate between mismatched data and blocked access, providing security without sacrificing the high-speed comparison capability of CAM architectures.
Solution Approach 2:
The patent segments the state space of the memory cell into distinct functional regions: standard data states (0, 1), wildcard state (BX), and blocking state (BB). This segmentation allows independent control of data storage, comparison flexibility, and security blocking functions, resolving the contradiction between security and state complexity.
2Reliability
If a blocking state is added to enhance security, then unauthorized access is prevented, but device complexity increases
Solution Approach 1:
The patent designs the memory cell to perform multiple functions using the same physical structure: data storage, wildcard matching, and security blocking. The blocking state serves dual purposes by both indicating security restrictions and participating in the comparison logic, eliminating the need for separate security circuitry and reducing overall device complexity.
Solution Approach 2:
The patent merges the security blocking function with the existing data comparison function by integrating the blocking state into the same state machine and comparison logic that handles 0, 1, and BX states. This consolidation allows security to be enforced without adding separate complex security circuits, maintaining device simplicity.
3Reliability
If blocking mode is used for mismatches, then pattern extraction difficulty increases, but impedance matching becomes more challenging
Solution Approach 1:
The patent employs the natural high-impedance state of the memory cell output to indicate blocking conditions. When a blocking state is detected during comparison, the output automatically transitions to a high-impedance state without requiring additional active control circuitry. This self-service approach uses the inherent electrical properties of the memory cell to provide security signaling, simplifying impedance control.
Data Source
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AI summary
A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the memory cell and the stored state of the memory cell are configured to be a plurality of states including a zero state, a one state, a no care state, and an input blocking state. When the input state of the memory cell is the blocking state, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is the no care state. When the stored state of the memory cell is the blocking state, the memory cell is configured to be in the blocking mode unless the input state of the memory cell is the no care state.