Word Line Voltage Equalization in NAND Flash Memory
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Solution Overview
Problem
In nonvolatile semiconductor storing apparatuses, such as NAND type flash memory, coupling noise between word lines and selecting gate lines increases due to advancements in micromachining, leading to potential errors and reduced reliability, especially during data writing operations.
Innovation Solution
A nonvolatile semiconductor memory device and method that includes a memory cell array with a cell string, word lines, selecting gates, and an equalizing unit that selects a target word line for writing and equalizes the voltages of all word lines after data writing is completed, reducing coupling noise by ensuring all word lines are at the same potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If micromachining technology is advanced to shorten distance between wirings, then integration density is improved, but coupling noise between word lines and selecting gate lines increases
Solution Approach 1:
The patent applies preliminary anti-action by equalizing the potentials of all word lines before the writing operation. By pre-charging or pre-discharging all word lines to the same potential level, the patent prevents potential differences from developing during the writing process, thereby counteracting the coupling noise that would otherwise be induced in non-selected word lines and selecting gate lines.
Solution Approach 2:
The patent implements equipotentiality by ensuring all word lines are maintained at the same potential through equalization circuits. This is achieved by connecting all word lines to a common potential reference and using equalization transistors to balance any potential differences, thereby eliminating the voltage gradients that cause coupling noise to propagate to adjacent wirings.
2Productivity
If voltage is applied to one word line for writing, then data write operation is performed, but coupling noise is generated in other word lines and selecting gate lines
Solution Approach 1:
The patent applies preliminary action by preparing all word lines in advance to the correct potential state before the actual writing operation begins. The equalization process occurs in a pre-charge phase, ensuring that when the write voltage is applied to the selected word line, no potential differences exist that could generate coupling noise in other lines.
Solution Approach 2:
The patent prevents coupling noise generation by establishing a uniform potential baseline across all word lines before writing. This preliminary anti-action ensures that the voltage transition in the selected word line does not induce noise in non-selected lines, as they are already at the reference potential.
3Ease of operation
If potential difference exists between word lines during writing, then selective writing is achieved, but erroneous operations occur due to coupling noise
Solution Approach 1:
The patent maintains equipotentiality among all word lines during non-selected states, ensuring they remain at the reference potential. The selective writing capability is achieved by applying voltage only to the specific selected word line through controlled switches, while all other lines remain equipotential, preventing coupling noise and ensuring reliable operation.
Solution Approach 2:
The patent applies local quality by creating a voltage difference only at the specific location of the selected word line, while all other word lines maintain the reference potential. This localized voltage application achieves selective writing without generating widespread coupling noise, as the potential difference is confined to only the necessary location.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of the cell string; and a drain side selecting gate connected to the other end of the cell string; a word line selector that selects one of the word lines connected to a target memory cell to be written; and an equalizing unit that equalizes voltages of the plurality of word lines after data write of the target memory cell is finished.