Analog-Digital Neural Array Using In-Situ Memory Synapses
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Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high-performance information processing due to a lack of adequate hardware technology, particularly in terms of high connectivity and energy efficiency, with CMOS-implemented synapses being too bulky for large-scale neural networks.
Innovation Solution
Utilizing non-volatile memory arrays as synapses in artificial neural networks, allowing for individual programming, erasing, and reading of memory cells without affecting others, and enabling continuous analog programming for precise tuning of synapse weights, thereby implementing vector-by-matrix multiplication arrays that perform in-situ memory computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS analog circuits are used for synapses to achieve high connectivity and parallelism, then computational capability is improved, but the area occupied by each synapse becomes too bulky for large-scale neural networks
Solution Approach 1:
The patent merges the storage function and computation function into a single memory cell. The memory cell stores weight values in its resistance state and directly performs multiplication with input signals during read operations, eliminating the need for separate multiplication circuits. This consolidation dramatically reduces the area per synapse while maintaining high computational capability through in-situ computation.
Solution Approach 2:
The patent replaces traditional CMOS analog circuitry with non-volatile memory cells (such as resistive memory cells) to implement synapses. This substitution uses the electrical resistance properties of memory materials to encode weights and perform computations, achieving higher density and lower area consumption compared to conventional CMOS-based analog circuits.
2Productivity
If digital supercomputers or GPU clusters are used to achieve high connectivity, then computational power is improved, but energy consumption increases significantly compared to biological networks
Solution Approach 1:
The memory cell performs computation during the normal read operation without requiring additional computational resources or energy-intensive processing. The multiplication of input signals with stored weights occurs naturally during the read process through Ohm's law, and the summation occurs naturally through Kirchhoff's current law at the bitline, making the system self-sufficient and energy-efficient.
Solution Approach 2:
The patent combines storage and computation into a single operation within the memory cell. Weight storage and synaptic multiplication are performed simultaneously using the same hardware resource (the memory cell itself), eliminating the need for separate storage and computation units that would increase energy consumption in traditional von Neumann architectures.
3Use of energy by moving object
If non-volatile memory arrays are used as synapses to enable in-situ computation, then energy efficiency is improved, but the ability to individually program and tune synapse weights must be maintained
Solution Approach 1:
The patent applies segmentation by dividing the programming process into fine-grained steps that can be applied to individual memory cells or small groups of cells. This allows precise control over each synapse weight while maintaining the overall array structure, enabling individual programming and tuning of synapses without requiring complex global control mechanisms.
Solution Approach 2:
The patent utilizes parameter changes in the memory cell resistance to encode different weight values. By controlling the resistance state of each memory cell through programmed changes (e.g., using pulse amplitude, width, or number of pulses), the system can individually tune synapse weights with high precision while maintaining energy-efficient in-situ computation.
Data Source
AI summary
Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples, an analog array and a digital array are coupled to separate bit lines.