Dual Word Line Preprogramming for NAND Data Retention
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in maintaining data retention due to vertical and lateral degradation, particularly when using negative word lines, which affect memory cell reliability.
Innovation Solution
Implementing a pre-programming pulse followed by a series of programming and verification pulses on selected and neighboring word lines to program and verify memory cells, utilizing a control means or controller to manage these pulses during program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If negative word lines are used in non-volatile memory, then manufacturing complexity is reduced, but data retention deteriorates due to vertical and lateral degradation
Solution Approach 1:
The patent applies pre-programming pulses to selected and neighboring word lines before the main programming operation. This preliminary action prepares the memory cells by reducing lateral degradation effects, thereby improving data retention without changing the negative word line structure itself. The pre-programming step creates a more favorable initial state for subsequent programming, mitigating the reliability issues caused by negative word lines.
Solution Approach 2:
The patent applies erase pulses to neighboring word lines before programming operations to counteract lateral degradation effects. This preliminary anti-action removes accumulated charge that would otherwise cause data retention problems during programming. By pre-cleaning the neighboring word lines, the system prevents the harmful lateral degradation from affecting the target memory cells.
2Reliability
If pre-programming pulses are applied to selected and neighboring word lines, then data retention is improved, but programming time increases
Solution Approach 1:
The patent applies pre-programming pulses only to selected and immediately neighboring word lines, rather than all word lines in the memory array. This partial application of the pre-programming action reduces the total time required compared to a full-array approach, while still providing sufficient degradation mitigation for the affected memory cells. The excessive action is limited to only what is necessary for reliable operation.
Solution Approach 2:
The patent implements pre-programming pulses as periodic operations that occur at specific intervals during memory operations, rather than continuously. The pre-programming is applied selectively before programming operations and before read operations on neighboring word lines, creating a periodic pattern that balances reliability improvement with time efficiency. This periodic application avoids unnecessary time consumption during operations where pre-programming is not required.
3Manufacturing precision
If multiple programming and verification pulses are applied, then programming precision is improved, but operation complexity increases
Solution Approach 1:
The patent implements verification pulses that read back the programmed data to confirm successful programming. This feedback mechanism allows the system to detect programming errors and determine whether re-programming is necessary. The verification step provides real-time information about programming success, enabling precise control over the programming process and ensuring high programming precision through iterative correction.
Solution Approach 2:
The patent applies pre-programming pulses to selected and neighboring word lines before the main programming operation. This preliminary action prepares the memory cells by reducing lateral degradation effects, thereby improving data retention without changing the negative word line structure itself. The pre-programming step creates a more favorable initial state for subsequent programming, mitigating the reliability issues caused by negative word lines.
Data Source
AI summary
A memory apparatus and operating method are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to apply a pre-programming pulse of a pre-program voltage to a selected one and at least one neighboring one of the plurality of word lines in a pre-program operation. The control means is also configured to apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the plurality of data states to the selected one of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation.