Flash Memory Write Suspension Using Saved Register Recovery
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Solution Overview
Problem
In semiconductor devices with multiple central processing units (CPUs) sharing a flash memory, competing writing and erasing operations lead to significant conflicts, necessitating the completion of lower-priority processes, which increases complexity and cost as the number of CPUs grows, especially when the number of CPU cores exceeds the number of memory banks.
Innovation Solution
Implementing additional circuits in the memory controller to manage and store writing data externally during suspended operations, allowing concurrent execution of writing and erasing tasks without completing lower-priority processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of CPU cores increases beyond the number of flash memory banks, then processing power increases, but operation competition and conflicts increase
Solution Approach 1:
The flash memory is divided into multiple banks that can operate independently and concurrently. Each bank can handle separate write or erase operations simultaneously, allowing multiple CPU cores to access different banks without conflict. This segmentation enables parallel processing while maintaining simple access control within each bank.
Solution Approach 2:
A memory controller is introduced as an intermediary between CPU cores and flash memory banks. The controller manages arbitration, tracks ongoing operations, and coordinates access to prevent conflicts. It maintains operation state information and manages the suspension/resumption of operations, reducing direct competition between CPU cores.
2Reliability
If lower-priority processes wait for completion, then data integrity is maintained, but response time increases
Solution Approach 1:
The system dynamically suspends and resumes write operations based on priority requirements. When a high-priority write operation is detected, the controller suspends lower-priority ongoing writes, allowing the high-priority operation to complete immediately. After resumption, the controller verifies data integrity to ensure reliability is maintained despite the dynamic switching.
Solution Approach 2:
The memory controller preliminarily tracks the state of ongoing write operations and prepares suspension points before conflicts occur. By maintaining operation state information in advance, the controller can quickly suspend and resume operations without extensive verification, reducing response time while ensuring data integrity through pre-established check mechanisms.
3Ease of manufacture
If flash memory divisions are reduced to lower cost, then manufacturing cost decreases, but operation competition increases
Solution Approach 1:
The flash memory is divided into multiple banks that can operate independently and concurrently. Each bank can handle separate write or erase operations simultaneously, allowing multiple CPU cores to access different banks without conflict. This segmentation enables parallel processing while maintaining simple access control within each bank.
Solution Approach 2:
Each flash memory bank is designed to be universally accessible by any CPU core through the memory controller. The banks can handle various operations (read, write, erase) and serve multiple masters, reducing the need for dedicated memory partitions for each CPU core and thereby lowering overall manufacturing cost.
4Productivity
If concurrent write and erase operations are enabled, then productivity increases, but control complexity increases
Solution Approach 1:
The flash memory is divided into multiple banks that can operate independently and concurrently. Each bank can handle separate write or erase operations simultaneously, allowing multiple CPU cores to access different banks without conflict. This segmentation enables parallel processing while maintaining simple access control within each bank.
Solution Approach 2:
The memory controller implements feedback mechanisms to monitor the state of each flash bank and dynamically adjust operation scheduling. By tracking ongoing operations and their completion status, the controller can safely enable concurrent operations across different banks while maintaining system consistency and preventing conflicts.
Data Source
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AI summary
A semiconductor device includes: a nonvolatile memory cell including first memory cells and second memory cells; a bit latch; and a saved register. In a first writing operation, first writing data are stored in the bit latch and the saved register, and writing to the first memory cells is executed based on the first writing data. During the first writing operation, the first writing operation is interrupted based on a suspension command, and a second writing operation is executed. In the second writing operation, second writing data are stored in the bit latch, and writing to the second memory cells is executed based on the second writing data. After the second writing operation is ended, the first writing data is reset to the bit latch based on a resume command, and the interrupted first writing operation is restarted based on the first writing data reset to the bit latch.