Stacked Memory Array Layout for Higher Capacity in Less Chip Area
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Solution Overview
Problem
There is a challenge in semiconductor memory devices to prevent an increase in chip area without compromising performance.
Innovation Solution
A semiconductor memory device is configured with a first chip containing a first memory cell array, a second chip with a second memory cell array, and a third chip with a row decoder and sense amplifier, where the memory cells are connected via a common word line and bit lines to a sense amplifier that can selectively read data from either array, allowing concurrent operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cell arrays are integrated on a single chip to increase storage capacity, then the storage capacity is improved, but the chip area increases
Solution Approach 1:
The patent divides the memory system into multiple independent chips, each containing a memory cell array. The first chip includes a first memory cell array, the second chip includes a second memory cell array, and the third chip includes control circuits. This segmentation allows multiple memory arrays to be distributed across separate chips rather than integrating them on a single chip, thereby increasing total storage capacity while avoiding the chip area expansion that would result from monolithic integration.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture. Multiple chips are stacked vertically and connected through inter-chip connections, enabling multiple memory cell arrays to coexist in the vertical dimension rather than competing for horizontal chip area. This dimensional transition resolves the contradiction by accommodating increased storage capacity without proportionally increasing the footprint of individual chips.
2Device complexity
If multiple memory cell arrays share common word lines to reduce wiring complexity, then the device complexity is reduced, but the ability to independently control memory operations is compromised
Solution Approach 1:
The patent assigns dedicated row decoders to specific memory cell arrays while sharing word line connections. The third chip includes a row decoder that can selectively control word lines for the first memory cell array, and separate control circuits on the second chip control word lines for the second memory cell array. This segmented control architecture maintains simple shared word line wiring while preserving independent operational capability through distributed decoder control.
Solution Approach 2:
The patent introduces control circuits on the second chip as intermediary elements that mediate between the shared word line infrastructure and the second memory cell array. These control circuits enable independent selection and control of the second memory cell array without interfering with operations on the first memory cell array, thus maintaining both wiring simplicity and operational independence.
3Device complexity
If a sense amplifier is shared between multiple memory cell arrays to reduce the number of sense amplifiers, then the device complexity is reduced, but the speed of concurrent read operations is limited
Solution Approach 1:
The patent assigns dedicated sense amplifiers to specific memory cell arrays through separate bit line connections. The first memory cell array connects to a first sense amplifier via a first bit line, while the second memory cell array connects to a second sense amplifier via a second bit line. This segmentation enables simultaneous read operations on both memory arrays at full speed, as each sense amplifier operates independently without contention for shared sensing resources.
Solution Approach 2:
The patent resolves the sense amplifier bottleneck by transitioning from a shared sensing resource model to a distributed sensing architecture. Multiple sense amplifiers are distributed across different chips and connected to different memory cell arrays through separate bit lines, enabling parallel read operations in the vertical dimension rather than sequential access through a single shared sense amplifier.
4Area of stationary object
If chips are stacked vertically to reduce the footprint area, then the area is reduced, but the inter-chip connection complexity increases
Solution Approach 1:
The patent segments the memory system into functionally distinct chips stacked vertically: the first chip contains a memory cell array, the second chip contains another memory cell array with control circuits, and the third chip contains control circuits. This functional segmentation simplifies inter-chip connections by establishing clear, dedicated signal paths between specific chips for specific operations, reducing the overall connection complexity despite the vertical stacking architecture.
Data Source
AI summary
A semiconductor memory device includes first, second, and third chips. The first chip includes a first memory cell. The second chip includes a second memory cell. The third chip includes a row decoder and a sense amplifier. The first and second memory cells are commonly connected to the row decoder via a first word line. The first and second memory cells are connected to the sense amplifier via first and second bit lines, respectively. The sense amplifier includes a first node selectively connectable to the first and second bit lines. The sense amplifier is configured to sense a voltage at the first node to read data in the first memory cell when the first node is connected to the first bit line and sense the voltage at the first node to read data in the second memory cell when the first node is connected to the second bit line.