NAND Flash Program Precharge for Faster Low-Interference Programming
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Solution Overview
Problem
The reduction in circuit area of NAND flash memory affects the ramping ability of memory array voltage, leading to increased programming time and programming interference due to reduced peripheral circuit loading, which is not effectively addressed by existing methods.
Innovation Solution
A program precharge process is implemented, applying specific voltage thresholds to bottom select gates and a common source to control the turn-on and turn-off of memory cell strings, reducing programming interference by attracting electrons to the common source and selectively turning off unselected memory cell strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the circuit area of NAND is reduced, then the storage capacity and cost efficiency are improved, but the ramping ability of memory array voltage deteriorates, resulting in increased programming time
Solution Approach 1:
The patent applies preliminary actions by pre-charging the common source to a first power supply voltage and pre-setting the bottom gate lines to specific voltages before the actual programming operation. This preliminary preparation ensures that when programming occurs, the voltage ramping is already optimized, compensating for the reduced ramping ability caused by smaller circuit area.
Solution Approach 2:
The patent changes voltage parameters dynamically during the programming process. It applies different voltages to different bottom gate lines (first bottom gate line receives second voltage, second bottom gate line receives third voltage) and adjusts the common source voltage in stages, optimizing the electric field distribution to improve voltage ramping speed despite the reduced circuit area.
2Quantity of substance
If the peripheral circuit area is reduced, then the storage density is improved, but the loading capability to drive memory array voltage deteriorates, resulting in increased programming time
Solution Approach 1:
The patent performs preliminary voltage application to the common source and bottom gate lines before the programming pulse is applied. This pre-charging action prepares the peripheral circuits to drive the memory array more effectively, compensating for the reduced loading capability caused by smaller peripheral circuit area.
Solution Approach 2:
The patent employs dynamic voltage control where the common source voltage transitions from a first power supply voltage during precharge to a second power supply voltage during programming. Different bottom gate lines receive different voltages dynamically, allowing the reduced peripheral circuits to effectively drive the memory array through optimized voltage timing and levels.
3Quantity of substance
If the circuit area is reduced, then the storage capacity is improved, but the voltage ramping ability deteriorates, resulting in increased programming interference
Solution Approach 1:
The patent applies local quality by treating different bottom gate lines differently - the first bottom gate line receives a second voltage while the second bottom gate line receives a third voltage. This localized voltage control creates optimal electric field conditions in specific regions, reducing programming interference caused by the reduced voltage ramping ability in the overall system.
Solution Approach 2:
The patent applies preliminary voltage settings to the common source and bottom gate lines before programming operations. This pre-charging to specific voltages ensures that when programming occurs, the voltage transitions are optimized, reducing the programming interference that would otherwise result from the reduced voltage ramping ability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces programming time and interference by optimizing the coupling potential of channels, thereby enhancing the efficiency of memory programming operations.
Implementation Method 1
applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line... The first voltage may be less than a first threshold voltage of a bottom select gate connected to the first bottom gate line, and the second voltage may be greater than a second threshold voltage of a bottom select gate connected to the second bottom gate line
Implementation Method 2
reducing programming interference by attracting electrons to the common source
Data Source
AI summary
According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.