PUF Memory Cell Layout for Unclonable Multi-Element Bit Storage
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Solution Overview
Problem
Existing physical unclonable functions (PUFs) in semiconductor devices lack sufficient security due to reliance on single memory elements for bit storage, making them vulnerable to unauthorized duplication and tampering.
Innovation Solution
Implementing memory devices with multiple memory elements in each cell, where each element has a unique state, ensuring only one is programmed per bit, and using distinct voltage levels to read these states, thereby enhancing security through increased complexity and unpredictability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple memory elements are used in each cell, then security is improved, but device complexity increases
Solution Approach 1:
The memory cell is segmented into multiple memory elements (first memory element and second memory element) within the same cell. Each element can be independently programmed to a specific state, creating multiple possible configurations per cell. This segmentation increases security by making it harder to determine the programmed state without significantly increasing overall device complexity through efficient layout integration.
2Reliability
If multiple states per bit are implemented, then unpredictability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Different memory elements within the same cell are assigned different local qualities or characteristics that enable them to be programmed to distinct states. The patent implements this by configuring at least one memory element to be programmable to a first state and another to a second state, creating local differentiation that enhances unpredictability while managing manufacturing precision through targeted programming approaches.
Data Source
AI summary
A method includes: programming a first bit of a physical unclonable function into a first memory cell; and generating, by a first memory circuit in the first memory cell, a first current indicating a logic value of the first bit. The programming the first bit includes: turning on a first switch in the first memory circuit and at least one second switch in at least one second memory circuit in the first memory cell in response to a first bit line signal, to program one of the first memory circuit and the at least one second memory circuit while rest of the first memory circuit and the at least one second memory circuit is not programmed, according to the first bit line signal. A memory device and a system are also disclosed herein.