Input Circuit Buffering Small Swing Signals in Non-Volatile Memory
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices have slow write speeds and struggle to properly buffer input signals with small swing ranges due to faster system bus transmission speeds, leading to improper buffering and signal integrity issues.
Innovation Solution
A non-volatile semiconductor memory device with an input circuit that trims reference voltage and clock signals using Mode Register Set (MRS) or electric fuse trim codes, generating buffered input signals through a reference voltage generating circuit, internal clock signal generating circuit, input buffer, and sampler, ensuring proper buffering of input signals with small swing ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If LVCMOS interface circuit is used for buffering input signal, then device complexity is reduced, but input signal with small swing range cannot be buffered properly
Solution Approach 1:
The patent changes the voltage level parameters of the input signal by providing multiple voltage levels (first voltage level for logic high, second voltage level for logic low) that are higher than the standard LVCMOS voltage levels. This parameter change allows the input signal to be properly buffered even with small swing ranges, while maintaining the simplicity of the LVCMOS interface circuit structure.
2Productivity
If system bus transmission speed is increased, then productivity is improved, but input signal swing range becomes smaller making buffering difficult
Solution Approach 1:
The patent addresses the reduced signal swing range caused by high-speed transmission by changing the voltage level parameters. The input buffer is designed to accept signals with larger voltage swings (first and second voltage levels) compared to standard LVCMOS levels, thereby maintaining reliable buffering capability even when the system bus operates at high speeds where signal degradation occurs.
3Ease of operation
If conventional input buffer is used, then ease of operation is maintained, but standby current cannot be reduced
Solution Approach 1:
The patent implements dynamic control of the input buffer by adding a control signal that can selectively enable or disable the buffer operation. This dynamic approach allows the input buffer to be turned off during standby periods when no data transmission is occurring, thereby reducing standby current consumption while maintaining ease of operation during active data transmission periods.
Data Source
AI summary
A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.