DQS Delay Alignment for Wider NAND Flash Read Margins
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Solution Overview
Problem
The reduction in effective width of data signals (DQ) and insufficient margins of setup and hold times due to changes in signal phase and width at the receive end, leading to data loss during high-speed reading and writing in storage systems, particularly in NFI bus connections between controllers and NAND flash memory.
Innovation Solution
Integration of a delay-locked loop (DLL) module and delay line (DL) into the controller to automatically adjust the timing relationship between DQ and DQS signals, aligning the DQS position at the center of the margin effective width to maximize setup and hold times, thereby preventing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the NFI bus rate is increased to improve storage device performance, then the IOPS increases, but the timing ratio decreases making timing adjustment more difficult
Solution Approach 1:
The system performs self-calibration by automatically adjusting DQS timing parameters based on measured signal characteristics. The controller autonomously determines optimal timing values without external intervention, enabling the system to adapt to high-speed operation conditions independently.
Solution Approach 2:
The invention dynamically adjusts timing parameters (setup time, hold time, sampling point) based on the operating conditions and signal quality. By changing these parameters adaptively, the system maintains reliable data transmission at higher bus rates where fixed timing would fail.
2Speed
If the bus rate is increased to improve performance, then the transmission speed increases, but the margin effective width of data signals is reduced
Solution Approach 1:
The system dynamically adjusts the DQS sampling point position and timing margins based on the actual signal conditions at different bus rates. This dynamic adaptation allows the system to maintain adequate timing margins even at higher speeds where signal integrity is more challenging.
Solution Approach 2:
The system uses feedback from signal quality measurements to adjust timing parameters. By monitoring the actual signal characteristics and adjusting DQS timing accordingly, the system maintains reliable operation across varying bus rates and environmental conditions.
3Productivity
If the bus rate is increased to improve performance, then the transmission speed increases, but the setup time and hold time margins become insufficient
Solution Approach 1:
The invention adjusts timing parameters including setup time and hold time margins based on the operating bus rate and signal conditions. By dynamically changing these parameters, the system maintains sufficient timing margins for reliable data latching even at higher transmission speeds.
4Reliability
If automatic timing adjustment is implemented to improve reliability, then the data transmission reliability increases, but the device complexity increases
Solution Approach 1:
The timing adjustment functionality is integrated into the existing controller architecture, allowing the same hardware resources to serve multiple functions. This approach improves reliability without proportionally increasing overall device complexity by reusing existing components for timing calibration.
Data Source
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AI summary
A data strobe signal DQS position adjustment method and apparatus are disclosed. The method includes: obtaining margin effective widths of all data signals DQs in a transmission bus; determining a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary; calculating a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training; and adjusting a delay line DL of the DQS to the first central position. According to this method, a margin of a setup time and a margin of a hold time in which a DQS samples a data signal at a first central position are maximized, thereby avoiding an error code during data reading and writing, and improving reliability of data read and write operations.